diff --git a/bsp/generated/TFT_Board.mex b/bsp/generated/TFT_Board.mex index f698e98..ac9e6f8 100644 --- a/bsp/generated/TFT_Board.mex +++ b/bsp/generated/TFT_Board.mex @@ -490,7 +490,7 @@ - + @@ -552,7 +552,7 @@ - + true diff --git a/bsp/generated/board/clock_config.c b/bsp/generated/board/clock_config.c index f554d10..4c4fba7 100644 --- a/bsp/generated/board/clock_config.c +++ b/bsp/generated/board/clock_config.c @@ -74,7 +74,7 @@ outputs: - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} - {id: LVDS1_CLK.outFreq, value: 1.2 GHz} -- {id: MQS_MCLK.outFreq, value: 2.8224 MHz} +- {id: MQS_MCLK.outFreq, value: 11.2896 MHz} - {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} - {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} @@ -135,7 +135,7 @@ settings: - {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} - {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} -- {id: IOMUXC_GPR.MQS_CLK_DIV.scale, value: '4', locked: true} +- {id: IOMUXC_GPR.MQS_CLK_DIV.scale, value: '1', locked: true} - {id: IOMUXC_GPR_GPR2_MQS_OVERSAMPLE, value: OverSampleRate64} sources: - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} @@ -481,7 +481,7 @@ void BOARD_BootClockRUN(void) /* Set SAI3 MCLK3 clock source. */ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate64, 3); + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate64, 0); /* Set ENET Ref clock source. */ #if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; diff --git a/bsp/generated/board/clock_config.h b/bsp/generated/board/clock_config.h index e71870e..17d53a6 100644 --- a/bsp/generated/board/clock_config.h +++ b/bsp/generated/board/clock_config.h @@ -65,7 +65,7 @@ void BOARD_InitBootClocks(void); #define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ #define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */ #define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL /* Clock consumers of LVDS1_CLK output : N/A */ -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 2822400UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 11289600UL /* Clock consumers of MQS_MCLK output : N/A */ #define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ #define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */ #define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ diff --git a/bsp/generated/clock_config.c b/bsp/generated/clock_config.c index f554d10..4c4fba7 100644 --- a/bsp/generated/clock_config.c +++ b/bsp/generated/clock_config.c @@ -74,7 +74,7 @@ outputs: - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} - {id: LVDS1_CLK.outFreq, value: 1.2 GHz} -- {id: MQS_MCLK.outFreq, value: 2.8224 MHz} +- {id: MQS_MCLK.outFreq, value: 11.2896 MHz} - {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} - {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} @@ -135,7 +135,7 @@ settings: - {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} - {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} -- {id: IOMUXC_GPR.MQS_CLK_DIV.scale, value: '4', locked: true} +- {id: IOMUXC_GPR.MQS_CLK_DIV.scale, value: '1', locked: true} - {id: IOMUXC_GPR_GPR2_MQS_OVERSAMPLE, value: OverSampleRate64} sources: - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} @@ -481,7 +481,7 @@ void BOARD_BootClockRUN(void) /* Set SAI3 MCLK3 clock source. */ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate64, 3); + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate64, 0); /* Set ENET Ref clock source. */ #if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; diff --git a/bsp/generated/clock_config.h b/bsp/generated/clock_config.h index e71870e..17d53a6 100644 --- a/bsp/generated/clock_config.h +++ b/bsp/generated/clock_config.h @@ -65,7 +65,7 @@ void BOARD_InitBootClocks(void); #define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ #define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */ #define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL /* Clock consumers of LVDS1_CLK output : N/A */ -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 2822400UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 11289600UL /* Clock consumers of MQS_MCLK output : N/A */ #define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ #define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */ #define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ diff --git a/bsp/mqs/src/mqs.c b/bsp/mqs/src/mqs.c index e89ae27..ac539d3 100644 --- a/bsp/mqs/src/mqs.c +++ b/bsp/mqs/src/mqs.c @@ -108,6 +108,11 @@ static void mqs_edma_callback(I2S_Type *p_base, sai_edma_handle_t *p_handle, sta /* -------------------------------------------------------------------------- * Публичный API * ----------------------------------------------------------------------- */ +/* + * AUDIO PLL setting: Frequency = Fref * (DIV_SELECT + NUM / DENOM) + * = 24 * (32 + 768/1000) + * = 786.432 MHz + */ bsp_status_t bsp_mqs_init(void) { @@ -119,13 +124,10 @@ bsp_status_t bsp_mqs_init(void) /* --- Тактирование SAI1 --- */ CLOCK_EnableClock(MQS_SAI_CLOCK_GATE); - /* --- Тактирование MQS (CCGR0[CG2]) — без него MQS не забирает данные из - * SAI FIFO и SAI_WriteBlocking зависает навсегда. --- */ + /* --- Тактирование MQS (CCGR0[CG2]) --- */ CLOCK_EnableClock(kCLOCK_Mqs); - /* --- MQS: сброс → включение. - * Oversample ×32 уже выставлен в BOARD_BootClockRUN(), - * повторный вызов IOMUXC_MQSConfig() не нужен. --- */ + /* --- MQS: сброс → включение --- */ IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR, true); IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR, false); IOMUXC_MQSEnable(IOMUXC_GPR, true); @@ -133,20 +135,14 @@ bsp_status_t bsp_mqs_init(void) /* --- SAI1: базовая инициализация (снимает reset, включает clock gate) --- */ SAI_Init(MQS_SAI_BASE); - /* --- SAI1 TX: классический I2S, master, 16 бит, стерео, канал 0. - * SAI_GetClassicI2SConfig() заполняет sai_transceiver_t значениями по - * умолчанию для стандартного I2S. Затем корректируем watermark и - * sync mode (async — TX не зависит от RX). --- */ + /* --- SAI1 TX: классический I2S, master, 16 бит, стерео, канал 0. --- */ sai_transceiver_t sai_cfg; SAI_GetLeftJustifiedConfig(&sai_cfg, kSAI_WordWidth16bits, kSAI_Stereo, (uint32_t) kSAI_Channel0Mask); - sai_cfg.syncMode = kSAI_ModeAsync; - sai_cfg.fifo.fifoWatermark = MQS_SAI_FIFO_WATERMARK; - sai_cfg.startChannel = 0; - - /* Явно задать источник bit clock — SAI1_CLK_ROOT (Mux делитель). - * Default после SAI_GetClassicI2SConfig может быть BusClock (IPG). */ + sai_cfg.syncMode = kSAI_ModeAsync; + sai_cfg.fifo.fifoWatermark = MQS_SAI_FIFO_WATERMARK; + sai_cfg.startChannel = 0; sai_cfg.bitClock.bclkSource = kSAI_BclkSourceMclkDiv; SAI_TxSetConfig(MQS_SAI_BASE, &sai_cfg); @@ -168,16 +164,11 @@ bsp_status_t bsp_mqs_init(void) DMAMUX_SetSource(DMAMUX, MQS_DMA_CHANNEL, (uint8_t) MQS_DMAMUX_SOURCE); DMAMUX_EnableChannel(DMAMUX, MQS_DMA_CHANNEL); - /* --- SAI eDMA handle + конфигурация. - * SAI_TransferTxSetConfigEDMA() — void, настраивает DMA-дескрипторы - * (размер minor loop, адрес FIFO) на основе sai_transceiver_t. --- */ + /* --- SAI eDMA handle + конфигурация --- */ SAI_TransferTxCreateHandleEDMA(MQS_SAI_BASE, &s_sai_tx_handle, mqs_edma_callback, NULL, &s_dma_handle); SAI_TransferTxSetConfigEDMA(MQS_SAI_BASE, &s_sai_tx_handle, &sai_cfg); - /* Включить SAI TX — без этого FIFO не дренируется даже в polling-режиме. - * SAI_TransferSendEDMA() включает его снова если MCUX_SDK_SAI_EDMA_TX_ENABLE_INTERNAL=1, - * но для корректной работы FIFO TX должен быть активен сразу после init. */ SAI_TxEnable(MQS_SAI_BASE, true); NVIC_SetPriority(DMA0_DMA16_IRQn, MQS_DMA_IRQ_PRIORITY); diff --git a/bsp/mqs/src/mqs_amp.c b/bsp/mqs/src/mqs_amp.c index 6c4fa0a..b3fd481 100644 --- a/bsp/mqs/src/mqs_amp.c +++ b/bsp/mqs/src/mqs_amp.c @@ -27,7 +27,6 @@ #include "bsp/mqs.h" #include "clock_config.h" -#include "fsl_clock.h" #include "fsl_pwm.h" #include "fsl_xbara.h" @@ -39,7 +38,7 @@ #define AMP_PWM_SUBMODULE kPWM_Module_0 #define AMP_PWM_CHANNEL kPWM_PwmA #define AMP_PWM_MODE kPWM_SignedCenterAligned -#define AMP_PWM_FREQ_HZ (16000U) +#define AMP_PWM_FREQ_HZ (12000U) /** Номинальный duty cycle при bsp_mqs_amp_init() — 50%. */ #define AMP_DEFAULT_DUTY (50U) @@ -104,6 +103,7 @@ bsp_status_t bsp_mqs_amp_init(void) .level = kPWM_HighTrue, .faultState = kPWM_PwmFaultState0, .deadtimeValue = 0U, + .pwmchannelenable = true, }; if (PWM_SetupPwm(AMP_PWM_BASE, AMP_PWM_SUBMODULE, &PWM_SIGNAL, 1U, AMP_PWM_MODE,