# bsp_sd: smoke test

bsp/generated/TFT_Board.mex

@@ -287,12 +287,12 @@
                         <data>true</data>
                      </feature>
                   </dependency>
-                  <dependency resourceType="Peripheral" resourceId="CMP1" description="Peripheral CMP1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitRS_UART_deinit">
+                  <dependency resourceType="Peripheral" resourceId="ADC1" description="Peripheral ADC1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitRS_UART_deinit">
                      <feature name="initialized" evaluation="equal">
                         <data>true</data>
                      </feature>
                   </dependency>
-                  <dependency resourceType="Peripheral" resourceId="ADC1" description="Peripheral ADC1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitRS_UART_deinit">
+                  <dependency resourceType="Peripheral" resourceId="CMP1" description="Peripheral CMP1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitRS_UART_deinit">
                      <feature name="initialized" evaluation="equal">
                         <data>true</data>
                      </feature>
@@ -351,12 +351,12 @@
                         <data>true</data>
                      </feature>
                   </dependency>
-                  <dependency resourceType="Peripheral" resourceId="CMP1" description="Peripheral CMP1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitRS_GPIO_deinit">
+                  <dependency resourceType="Peripheral" resourceId="ADC1" description="Peripheral ADC1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitRS_GPIO_deinit">
                      <feature name="initialized" evaluation="equal">
                         <data>true</data>
                      </feature>
                   </dependency>
-                  <dependency resourceType="Peripheral" resourceId="ADC1" description="Peripheral ADC1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitRS_GPIO_deinit">
+                  <dependency resourceType="Peripheral" resourceId="CMP1" description="Peripheral CMP1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitRS_GPIO_deinit">
                      <feature name="initialized" evaluation="equal">
                         <data>true</data>
                      </feature>
@@ -488,7 +488,7 @@
                   <clock_output id="IPG_CLK_ROOT.outFreq" value="150 MHz" locked="false" accuracy=""/>
                   <clock_output id="LCDIF_CLK_ROOT.outFreq" value="3 MHz" locked="false" accuracy=""/>
                   <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
-                  <clock_output id="LPSPI_CLK_ROOT.outFreq" value="6 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
                   <clock_output id="LVDS1_CLK.outFreq" value="1.2 GHz" locked="false" accuracy=""/>
                   <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
                   <clock_output id="PERCLK_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
@@ -505,23 +505,36 @@
                   <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
                   <clock_output id="SEMC_CLK_ROOT.outFreq" value="120 MHz" locked="false" accuracy=""/>
                   <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
-                  <clock_output id="TRACE_CLK_ROOT.outFreq" value="6 MHz" locked="false" accuracy=""/>
+                  <clock_output id="TRACE_CLK_ROOT.outFreq" value="99 MHz" locked="false" accuracy=""/>
                   <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
                   <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
-                  <clock_output id="USDHC1_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC1_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
-                  <clock_output id="USDHC2_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC2_CLK_ROOT.outFreq" value="79.2 MHz" locked="false" accuracy=""/>
                </clock_outputs>
                <clock_settings>
                   <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
                   <setting id="CCM.ARM_PODF.scale" value="2" locked="true"/>
                   <setting id="CCM.CAN_CLK_PODF.scale" value="1" locked="true"/>
                   <setting id="CCM.LCDIF_PRE_CLK_SEL.sel" value="CCM_ANALOG.PLL5_MAIN_CLK" locked="false"/>
+                  <setting id="CCM.LPSPI_PODF.scale" value="5" locked="false"/>
                   <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
                   <setting id="CCM.PERIPH_CLK2_SEL.sel" value="XTALOSC24M.OSC_CLK" locked="false"/>
                   <setting id="CCM.SEMC_PODF.scale" value="5" locked="true"/>
+                  <setting id="CCM.USDHC1_CLK_SEL.sel" value="CCM_ANALOG.PLL2_PFD0_CLK" locked="false"/>
+                  <setting id="CCM.USDHC1_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.USDHC2_PODF.scale" value="5" locked="false"/>
                   <setting id="CCM_ANALOG.PLL1_BYPASS.sel" value="CCM_ANALOG.PLL1" locked="false"/>
                   <setting id="CCM_ANALOG.PLL1_PREDIV.scale" value="1" locked="true"/>
                   <setting id="CCM_ANALOG.PLL1_VDIV.scale" value="50" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2.num" value="0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD0_DIV.scale" value="24" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD0_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
                   <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
                   <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
                   <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>

bsp/generated/board.c

@@ -97,9 +97,18 @@ static void board_mpu_init(void)
     SCB_EnableICache();
 }
 
+static void board_dwt_init(void)
+{
+    /* DWT cycle counter — нужен для точного SDK_DelayAtLeastUs.
+     * Без этого SDK использует software loop с непредсказуемым timing. */
+    CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+    DWT->CYCCNT = 0U;
+    DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
+}
+
 void board_hw_init(void)
 {
-
+    board_dwt_init();
     BOARD_InitPins();
     BOARD_BootClockRUN();
     board_mpu_init();

bsp/generated/board/clock_config.c

@@ -72,7 +72,7 @@ outputs:
 - {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
 - {id: LCDIF_CLK_ROOT.outFreq, value: 3 MHz}
 - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
-- {id: LPSPI_CLK_ROOT.outFreq, value: 6 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
 - {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
 - {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
 - {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
@@ -89,22 +89,35 @@ outputs:
 - {id: SAI3_MCLK3.outFreq, value: 30 MHz}
 - {id: SEMC_CLK_ROOT.outFreq, value: 120 MHz}
 - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
-- {id: TRACE_CLK_ROOT.outFreq, value: 6 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 99 MHz}
 - {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
 - {id: USBPHY1_CLK.outFreq, value: 480 MHz}
-- {id: USDHC1_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
-- {id: USDHC2_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 79.2 MHz}
 settings:
 - {id: CCM.AHB_PODF.scale, value: '1', locked: true}
 - {id: CCM.ARM_PODF.scale, value: '2', locked: true}
 - {id: CCM.CAN_CLK_PODF.scale, value: '1', locked: true}
 - {id: CCM.LCDIF_PRE_CLK_SEL.sel, value: CCM_ANALOG.PLL5_MAIN_CLK}
+- {id: CCM.LPSPI_PODF.scale, value: '5'}
 - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
 - {id: CCM.PERIPH_CLK2_SEL.sel, value: XTALOSC24M.OSC_CLK}
 - {id: CCM.SEMC_PODF.scale, value: '5', locked: true}
+- {id: CCM.USDHC1_CLK_SEL.sel, value: CCM_ANALOG.PLL2_PFD0_CLK}
+- {id: CCM.USDHC1_PODF.scale, value: '2', locked: true}
+- {id: CCM.USDHC2_PODF.scale, value: '5'}
 - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
 - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
 - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1'}
+- {id: CCM_ANALOG.PLL2.num, value: '0'}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD0_DIV.scale, value: '24', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
 - {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
 - {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
 - {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
@@ -128,8 +141,8 @@ const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
 const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
     {
         .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
-        .numerator = 1,                           /* 30 bit numerator of fractional loop divider */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
-        .denominator = 60000,                     /* 30 bit denominator of fractional loop divider */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
         .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
     };
 const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
@@ -201,11 +214,11 @@ void BOARD_BootClockRUN(void)
     /* Set USDHC1_PODF. */
     CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
     /* Set Usdhc1 clock source. */
-    CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+    CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1);
     /* Disable USDHC2 clock gate. */
     CLOCK_DisableClock(kCLOCK_Usdhc2);
     /* Set USDHC2_PODF. */
-    CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+    CLOCK_SetDiv(kCLOCK_Usdhc2Div, 4);
     /* Set Usdhc2 clock source. */
     CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
     /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
@@ -244,7 +257,7 @@ void BOARD_BootClockRUN(void)
     CLOCK_DisableClock(kCLOCK_Lpspi3);
     CLOCK_DisableClock(kCLOCK_Lpspi4);
     /* Set LPSPI_PODF. */
-    CLOCK_SetDiv(kCLOCK_LpspiDiv, 3);
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
     /* Set Lpspi clock source. */
     CLOCK_SetMux(kCLOCK_LpspiMux, 2);
     /* Disable TRACE clock gate. */
@@ -353,15 +366,13 @@ void BOARD_BootClockRUN(void)
     /* Init System PLL. */
     CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
     /* Init System pfd0. */
-    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 24);
     /* Init System pfd1. */
     CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
     /* Init System pfd2. */
     CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
     /* Init System pfd3. */
     CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
-    /* Bypass System PLL. */
-    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllSys, 1);
 #endif
     /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
      * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.

bsp/generated/board/clock_config.h

@@ -63,7 +63,7 @@ void BOARD_InitBootClocks(void);
 #define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               150000000UL    /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, EWM, FLEXIO1, FLEXIO2, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */
 #define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT             3000000UL      /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */
 #define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL     /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */
-#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             6000000UL      /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL    /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */
 #define BOARD_BOOTCLOCKRUN_LVDS1_CLK                  1200000000UL   /* Clock consumers of LVDS1_CLK output : N/A */
 #define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL     /* Clock consumers of MQS_MCLK output : N/A */
 #define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            75000000UL     /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */
@@ -83,12 +83,12 @@ void BOARD_InitBootClocks(void);
 #define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT              120000000UL    /* Clock consumers of SEMC_CLK_ROOT output : SEMC */
 #define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL     /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */
 #define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL            /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */
-#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             6000000UL      /* Clock consumers of TRACE_CLK_ROOT output : ARM */
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             99000000UL     /* Clock consumers of TRACE_CLK_ROOT output : ARM */
 #define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL     /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */
 #define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                480000000UL    /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */
 #define BOARD_BOOTCLOCKRUN_USBPHY2_CLK                0UL            /* Clock consumers of USBPHY2_CLK output : USB2 */
-#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            12000000UL     /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            198000000UL    /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
-#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            12000000UL     /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            79200000UL     /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
 
 /*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
  */

bsp/generated/board/pin_mux.h

@@ -267,16 +267,16 @@ void BOARD_InitRS_UART(void);
 
 /* GPIO_AD_B1_07 (coord K10), RsRx */
 /* Routed pin properties */
-#define BOARD_INITRS_UART_DEINIT_RsRx_PERIPHERAL                            CMP1   /*!< Peripheral name */
-#define BOARD_INITRS_UART_DEINIT_RsRx_SIGNAL                                  IN   /*!< Signal name */
-#define BOARD_INITRS_UART_DEINIT_RsRx_CHANNEL                                 5U   /*!< Signal channel */
-
-/* GPIO_AD_B1_07 (coord K10) */
-/* Routed pin properties */
 #define BOARD_INITRS_UART_DEINIT_RsRx_PERIPHERAL                            ADC1   /*!< Peripheral name */
 #define BOARD_INITRS_UART_DEINIT_RsRx_SIGNAL                                  IN   /*!< Signal name */
 #define BOARD_INITRS_UART_DEINIT_RsRx_CHANNEL                                12U   /*!< Signal channel */
 
+/* GPIO_AD_B1_07 (coord K10) */
+/* Routed pin properties */
+#define BOARD_INITRS_UART_DEINIT_RsRx_PERIPHERAL                            CMP1   /*!< Peripheral name */
+#define BOARD_INITRS_UART_DEINIT_RsRx_SIGNAL                                  IN   /*!< Signal name */
+#define BOARD_INITRS_UART_DEINIT_RsRx_CHANNEL                                 5U   /*!< Signal channel */
+
 
 /*!
  * @brief This is a de-initialization function for 'BOARD_InitRS_UART' function.
@@ -329,16 +329,16 @@ void BOARD_InitRS_GPIO(void);
 
 /* GPIO_AD_B1_07 (coord K10), RsRx */
 /* Routed pin properties */
-#define BOARD_INITRS_GPIO_DEINIT_RsRx_PERIPHERAL                            CMP1   /*!< Peripheral name */
-#define BOARD_INITRS_GPIO_DEINIT_RsRx_SIGNAL                                  IN   /*!< Signal name */
-#define BOARD_INITRS_GPIO_DEINIT_RsRx_CHANNEL                                 5U   /*!< Signal channel */
-
-/* GPIO_AD_B1_07 (coord K10) */
-/* Routed pin properties */
 #define BOARD_INITRS_GPIO_DEINIT_RsRx_PERIPHERAL                            ADC1   /*!< Peripheral name */
 #define BOARD_INITRS_GPIO_DEINIT_RsRx_SIGNAL                                  IN   /*!< Signal name */
 #define BOARD_INITRS_GPIO_DEINIT_RsRx_CHANNEL                                12U   /*!< Signal channel */
 
+/* GPIO_AD_B1_07 (coord K10) */
+/* Routed pin properties */
+#define BOARD_INITRS_GPIO_DEINIT_RsRx_PERIPHERAL                            CMP1   /*!< Peripheral name */
+#define BOARD_INITRS_GPIO_DEINIT_RsRx_SIGNAL                                  IN   /*!< Signal name */
+#define BOARD_INITRS_GPIO_DEINIT_RsRx_CHANNEL                                 5U   /*!< Signal channel */
+
 
 /*!
  * @brief This is a de-initialization function for 'BOARD_InitRS_GPIO' function.

bsp/generated/clock_config.c

@@ -72,7 +72,7 @@ outputs:
 - {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
 - {id: LCDIF_CLK_ROOT.outFreq, value: 3 MHz}
 - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
-- {id: LPSPI_CLK_ROOT.outFreq, value: 6 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
 - {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
 - {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
 - {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
@@ -89,26 +89,42 @@ outputs:
 - {id: SAI3_MCLK3.outFreq, value: 30 MHz}
 - {id: SEMC_CLK_ROOT.outFreq, value: 120 MHz}
 - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
-- {id: TRACE_CLK_ROOT.outFreq, value: 6 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 99 MHz}
 - {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
-- {id: USDHC1_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
-- {id: USDHC2_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 79.2 MHz}
 settings:
 - {id: CCM.AHB_PODF.scale, value: '1', locked: true}
 - {id: CCM.ARM_PODF.scale, value: '2', locked: true}
 - {id: CCM.CAN_CLK_PODF.scale, value: '1', locked: true}
 - {id: CCM.LCDIF_PRE_CLK_SEL.sel, value: CCM_ANALOG.PLL5_MAIN_CLK}
+- {id: CCM.LPSPI_PODF.scale, value: '5'}
 - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
 - {id: CCM.PERIPH_CLK2_SEL.sel, value: XTALOSC24M.OSC_CLK}
 - {id: CCM.SEMC_PODF.scale, value: '5', locked: true}
+- {id: CCM.USDHC1_CLK_SEL.sel, value: CCM_ANALOG.PLL2_PFD0_CLK}
+- {id: CCM.USDHC1_PODF.scale, value: '2', locked: true}
+- {id: CCM.USDHC2_PODF.scale, value: '5'}
 - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
 - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
 - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1'}
+- {id: CCM_ANALOG.PLL2.num, value: '0'}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD0_DIV.scale, value: '24', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
 - {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
 - {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
 - {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
 - {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
 - {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
 - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
 sources:
 - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
@@ -125,8 +141,8 @@ const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
 const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
     {
         .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
-        .numerator = 1,                           /* 30 bit numerator of fractional loop divider */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
-        .denominator = 60000,                     /* 30 bit denominator of fractional loop divider */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
         .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
     };
 const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
@@ -198,11 +214,11 @@ void BOARD_BootClockRUN(void)
     /* Set USDHC1_PODF. */
     CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
     /* Set Usdhc1 clock source. */
-    CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+    CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1);
     /* Disable USDHC2 clock gate. */
     CLOCK_DisableClock(kCLOCK_Usdhc2);
     /* Set USDHC2_PODF. */
-    CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+    CLOCK_SetDiv(kCLOCK_Usdhc2Div, 4);
     /* Set Usdhc2 clock source. */
     CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
     /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
@@ -241,7 +257,7 @@ void BOARD_BootClockRUN(void)
     CLOCK_DisableClock(kCLOCK_Lpspi3);
     CLOCK_DisableClock(kCLOCK_Lpspi4);
     /* Set LPSPI_PODF. */
-    CLOCK_SetDiv(kCLOCK_LpspiDiv, 3);
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
     /* Set Lpspi clock source. */
     CLOCK_SetMux(kCLOCK_LpspiMux, 2);
     /* Disable TRACE clock gate. */
@@ -350,15 +366,13 @@ void BOARD_BootClockRUN(void)
     /* Init System PLL. */
     CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
     /* Init System pfd0. */
-    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 24);
     /* Init System pfd1. */
     CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
     /* Init System pfd2. */
     CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
     /* Init System pfd3. */
     CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
-    /* Bypass System PLL. */
-    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllSys, 1);
 #endif
     /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
      * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
@@ -374,8 +388,6 @@ void BOARD_BootClockRUN(void)
     CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
     /* Init Usb1 pfd3. */
     CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
-    /* Disable Usb1 PLL output for USBPHY1. */
-    CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
 #endif
     /* DeInit Audio PLL. */
     CLOCK_DeinitAudioPll();

bsp/generated/clock_config.h

@@ -63,7 +63,7 @@ void BOARD_InitBootClocks(void);
 #define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               150000000UL    /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, EWM, FLEXIO1, FLEXIO2, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */
 #define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT             3000000UL      /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */
 #define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL     /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */
-#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             6000000UL      /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL    /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */
 #define BOARD_BOOTCLOCKRUN_LVDS1_CLK                  1200000000UL   /* Clock consumers of LVDS1_CLK output : N/A */
 #define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL     /* Clock consumers of MQS_MCLK output : N/A */
 #define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            75000000UL     /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */
@@ -83,12 +83,12 @@ void BOARD_InitBootClocks(void);
 #define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT              120000000UL    /* Clock consumers of SEMC_CLK_ROOT output : SEMC */
 #define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL     /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */
 #define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL            /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */
-#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             6000000UL      /* Clock consumers of TRACE_CLK_ROOT output : ARM */
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             99000000UL     /* Clock consumers of TRACE_CLK_ROOT output : ARM */
 #define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL     /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */
-#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                0UL            /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                480000000UL    /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */
 #define BOARD_BOOTCLOCKRUN_USBPHY2_CLK                0UL            /* Clock consumers of USBPHY2_CLK output : USB2 */
-#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            12000000UL     /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            198000000UL    /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
-#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            12000000UL     /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            79200000UL     /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
 
 /*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
  */

bsp/generated/sdmmc_config.c

@@ -24,6 +24,15 @@ static sd_io_voltage_t s_io_voltage = {
     .func = NULL, /* управление через регистры USDHC, не через внешний LDO */
 };
 
+/* Debug markers for runtime verification in debugger. */
+volatile uint32_t g_sdmmc_dbg_dma_buf_addr         = 0U;
+volatile uint32_t g_sdmmc_dbg_usdhc1_src_clock_hz  = 0U;
+
+static bool sd_card_detect_gpio(void)
+{
+    return GPIO_PinRead(BOARD_SDMMC_SD_CD_GPIO_BASE, BOARD_SDMMC_SD_CD_GPIO_PIN) == BOARD_SDMMC_SD_CD_INSERT_LEVEL;
+}
+
 /* ---------------------------------------------------------------------------
  * Внутренние функции
  * ------------------------------------------------------------------------- */
@@ -36,7 +45,7 @@ static sd_io_voltage_t s_io_voltage = {
  */
 static uint32_t get_usdhc1_src_clock_hz(void)
 {
-    return BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT; /* 198 000 000 Hz */
+    return BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT;
 }
 
 /*
@@ -44,7 +53,11 @@ static uint32_t get_usdhc1_src_clock_hz(void)
  */
 static void sd_power_control(bool enable)
 {
+#if BOARD_SDMMC_SD_PWR_ACTIVE_HIGH
     GPIO_PinWrite(BOARD_SDMMC_SD_PWR_GPIO_BASE, BOARD_SDMMC_SD_PWR_GPIO_PIN, enable ? 1U : 0U);
+#else
+    GPIO_PinWrite(BOARD_SDMMC_SD_PWR_GPIO_BASE, BOARD_SDMMC_SD_PWR_GPIO_PIN, enable ? 0U : 1U);
+#endif
 }
 
 /*
@@ -55,7 +68,11 @@ static void sd_power_init(void)
 {
     const gpio_pin_config_t cfg = {
         .direction     = kGPIO_DigitalOutput,
+#if BOARD_SDMMC_SD_PWR_ACTIVE_HIGH
         .outputLogic   = 0U, /* питание выключено при старте */
+#else
+        .outputLogic   = 1U, /* питание выключено при старте */
+#endif
         .interruptMode = kGPIO_NoIntmode,
     };
     GPIO_PinInit(BOARD_SDMMC_SD_PWR_GPIO_BASE, BOARD_SDMMC_SD_PWR_GPIO_PIN, &cfg);
@@ -106,6 +123,10 @@ static void sd_pin_config(uint32_t freq)
     IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, pad);
     IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, pad);
     IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, pad);
+    /* CD_B в GPIO-режиме: подтяжка вверх + hysteresis для стабильного уровня. */
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_12_GPIO2_IO28,
+                        IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1));
 }
 
 /* ---------------------------------------------------------------------------
@@ -127,11 +148,13 @@ void BOARD_SD_Config(void *card, sd_cd_t cd, uint32_t host_irq_priority, void *u
     sd->host                                = &s_host;
     sd->host->hostController.base           = BOARD_SDMMC_SD_HOST_BASEADDR;
     sd->host->hostController.sourceClock_Hz = get_usdhc1_src_clock_hz();
+    g_sdmmc_dbg_dma_buf_addr                = (uint32_t)(uintptr_t)s_dma_buf;
+    g_sdmmc_dbg_usdhc1_src_clock_hz         = sd->host->hostController.sourceClock_Hz;
 
-    /* --- card detect: HostCD, GPIO-прерывание не нужно --- */
+    /* --- card detect: GPIO CD (active-low) --- */
     s_cd.cdDebounce_ms = BOARD_SDMMC_SD_CD_DEBOUNCE_MS;
-    s_cd.type          = BOARD_SDMMC_SD_CD_TYPE; /* kSD_DetectCardByHostCD */
+    s_cd.type          = BOARD_SDMMC_SD_CD_TYPE;
-    s_cd.cardDetected  = NULL; /* SDK читает PRSSTAT самостоятельно */
+    s_cd.cardDetected  = sd_card_detect_gpio;
     s_cd.callback      = cd;   /* обычно NULL из bsp_sd */
     s_cd.userData      = user_data;
 
@@ -143,6 +166,16 @@ void BOARD_SD_Config(void *card, sd_cd_t cd, uint32_t host_irq_priority, void *u
 
     /* --- GPIO питания --- */
     sd_power_init();
+    /* CD_B: переводим в GPIO2_IO28 и настраиваем вход */
+    IOMUXC_SetPinMux(IOMUXC_GPIO_B1_12_GPIO2_IO28, 0U);
+    const gpio_pin_config_t cd_cfg = {
+        .direction     = kGPIO_DigitalInput,
+        .outputLogic   = 0U,
+        .interruptMode = kGPIO_NoIntmode,
+    };
+    GPIO_PinInit(BOARD_SDMMC_SD_CD_GPIO_BASE, BOARD_SDMMC_SD_CD_GPIO_PIN, &cd_cfg);
+    /* Важно: применяем pad-конфиг сразу для ранних CMD (CMD0/CMD8/CMD55/ACMD41). */
+    sd_pin_config(400000U);
 
     /* --- приоритет прерывания хоста --- */
     NVIC_SetPriority(BOARD_SDMMC_SD_HOST_IRQ, host_irq_priority);

bsp/generated/sdmmc_config.h

@@ -1,9 +1,8 @@
 /*
  * sdmmc_config.h — board-level конфигурация SDMMC для MIMXRT1052CVJ5B.
  *
- * SD_CD : GPIO_B1_12 → USDHC1.usdhc_cd_b (периферийный сигнал, не GPIO).
+ * SD_CD : GPIO_B1_12 → GPIO2[28] (GPIO card detect).
- *         Детект через USDHC_GetPresentStatusFlags → kSD_DetectCardByHostCD.
+ *         Уровень вставки карты: 0 (active-low).
- *         GPIO-прерывание на CD не нужно.
  *
  * SD_PWR: GPIO_AD_B1_03 → GPIO1[19] (SdPwr).
  *         Active-high: 1 = питание включено.
@@ -34,7 +33,10 @@
  * CD_B подключён как периферийный сигнал USDHC1 — детект через регистр
  * PRSSTAT, а не через GPIO. Прерывание и callback на CD не используются.
  * ------------------------------------------------------------------------- */
-#define BOARD_SDMMC_SD_CD_TYPE        kSD_DetectCardByHostCD
+#define BOARD_SDMMC_SD_CD_GPIO_BASE    GPIO2
+#define BOARD_SDMMC_SD_CD_GPIO_PIN     28U
+#define BOARD_SDMMC_SD_CD_INSERT_LEVEL 0U
+#define BOARD_SDMMC_SD_CD_TYPE         kSD_DetectCardByGpioCD
 #define BOARD_SDMMC_SD_CD_DEBOUNCE_MS  100U
 
 /* ---------------------------------------------------------------------------
@@ -42,11 +44,17 @@
  * ------------------------------------------------------------------------- */
 #define BOARD_SDMMC_SD_PWR_GPIO_BASE GPIO1
 #define BOARD_SDMMC_SD_PWR_GPIO_PIN  19U
+/* 1U: питание карты включается уровнем '1'; 0U: включается уровнем '0'. */
+#define BOARD_SDMMC_SD_PWR_ACTIVE_HIGH 0U
 
 /* ---------------------------------------------------------------------------
  * IO voltage — управляется хостом (LDO внутри USDHC)
  * ------------------------------------------------------------------------- */
-#define BOARD_SDMMC_SD_IO_VOLTAGE_TYPE kSD_IOVoltageCtrlByHost
+/*
+ * На данной плате для SD-стека отключаем процедуру переключения на 1.8V
+ * (CMD11/UHS voltage switch): SD_Init продолжит работу в 3.3V режиме.
+ */
+#define BOARD_SDMMC_SD_IO_VOLTAGE_TYPE kSD_IOVoltageCtrlNotSupport
 
 /* ---------------------------------------------------------------------------
  * DMA и кэш

bsp/sd/README.md

@@ -43,8 +43,8 @@ sdk_usdhc                    ← NXP HAL: fsl_usdhc
 | CLK      | GPIO_SD_B0_01   | USDHC1_CLK, периферийный режим                    |
 | CMD      | GPIO_SD_B0_00   | USDHC1_CMD, периферийный режим                    |
 | D0–D3    | GPIO_SD_B0_02–05| USDHC1_DATA0–3, периферийный режим                |
-| CD_B     | GPIO_B1_12      | USDHC1_CD_B — детект через USDHC PRSSTAT          |
+| CD_B     | GPIO_B1_12      | USDHC1_CD_B — детект через GPIO2[28]              |
-| SdPwr    | GPIO_AD_B1_03   | GPIO1[19], active-high, управляется SDK через BSP |
+| SdPwr    | GPIO_AD_B1_03   | GPIO1[19], active-low, управляется SDK через BSP  |
 
 **CD_B** подключён как периферийный сигнал USDHC1, а не как GPIO. Детект карты
 читается через `USDHC_GetPresentStatusFlags` → `kUSDHC_CardInsertedFlag`.
@@ -93,12 +93,12 @@ host-контроллер (`SD_HostInit`).
 ## Разделение ответственности: bsp_sd vs sdmmc_config vs port_fatfs_sd
 
 | Слой                  | Что делает                                              | Где живёт                          |
-|-----------------------|---------------------------------------------------------|------------------------|
+|-----------------------|---------------------------------------------------------|------------------------------------|
 | `sdmmc_config`        | Константы платы, `BOARD_SD_Config`, GPIO питания, pads  | `bsp/generated/`                   |
 | `bsp_sd`              | `SD_HostInit/Deinit`, идемпотентность, card detect      | `bsp/sd/`                          |
 | `port_fatfs_sd`       | `microsd_disk_*` → `fsl_sd_disk` (FatFS diskio glue)    | `port/fatfs/sd/`                   |
-| `firmware_test_fatfs` | `ff.c` + `fsl_sd_disk` + `diskio.c` (bare-metal ffconf)| `firmware/test/fatfs/` |
+| `firmware_test_fatfs` | `ff.c` + `fsl_sd_disk` + `diskio.c` (bare-metal ffconf) | `firmware/test/fatfs/`             |
-| `tft_app_fatfs`       | `ff.c` + `fsl_sd_disk` + `diskio.c` (FreeRTOS ffconf)  | `firmware/tft_app/fatfs/` (будущее) |
+| `tft_app_fatfs`       | `ff.c` + `fsl_sd_disk` + `diskio.c` (FreeRTOS ffconf)   | `firmware/tft_app/fatfs/` (будущее)|
 
 **Почему `ff.c` и `fsl_sd_disk.c` не компилируются один раз как общая библиотека:**
 оба включают `ff.h` → `ffconf.h`, который разный для `firmware_test` (bare-metal,

bsp/sd/src/sd.c

@@ -4,7 +4,6 @@
 
 #include "bsp/sd.h"
 
-#include "fsl_clock.h"
 #include "fsl_sd.h"
 #include "sdmmc_config.h" /* BOARD_SD_Config, BOARD_SDMMC_SD_HOST_BASEADDR */
 
@@ -74,20 +73,12 @@ bsp_status_t bsp_sd_deinit(void)
     SD_SetCardPower(&g_sd, false);
 
     g_s_initialized     = false;
+    g_s_host_configured = false;
     return BSP_OK;
 }
 
 bool bsp_sd_is_inserted(void)
 {
-    /*
+    return GPIO_PinRead(BOARD_SDMMC_SD_CD_GPIO_BASE, BOARD_SDMMC_SD_CD_GPIO_PIN) ==
-     * CD_B подключён как периферийный сигнал USDHC1, поэтому детект —
+           BOARD_SDMMC_SD_CD_INSERT_LEVEL;
-     * через регистр PRSSTAT, а не GPIO.
-     *
-     * USDHC1 может быть ещё не тактирован в момент вызова (до init),
-     * поэтому явно включаем clock. После init clock уже включён SDK-стеком,
-     * повторный вызов CLOCK_EnableClock безвреден.
-     */
-    CLOCK_EnableClock(kCLOCK_Usdhc1);
-    uint32_t prsstat = USDHC_GetPresentStatusFlags(BOARD_SDMMC_SD_HOST_BASEADDR);
-    return (prsstat & (uint32_t) kUSDHC_CardInsertedFlag) != 0U;
 }

firmware/test/fatfs/src/diskio.c

@@ -1,7 +1,7 @@
 /*
  * diskio.c — FatFS diskio диспетчер для firmware_test.
  *
- * FF_VOLUMES=1: единственный диск "0:/" = SDDISK.
+ * FF_VOLUMES=3: диски 0 и 1 — заглушки, диск 2 = SDDISK (microSD).
  * W25Q и RAM-диск отсутствуют — нет зависимости на bsp_qspi_flash.
  */
 

sdk/CMakeLists.txt

@@ -37,7 +37,8 @@ add_library(sdk_common STATIC devices/MIMXRT1052/drivers/fsl_common.c
                               devices/MIMXRT1052/drivers/fsl_common_arm.c)
 target_include_directories(sdk_common PUBLIC devices/MIMXRT1052/drivers)
 target_compile_definitions(
-  sdk_common PUBLIC SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY=600000000U)
+  sdk_common PUBLIC SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY=600000000U
+                    SDK_DELAY_USE_DWT)
 target_link_libraries(sdk_common PUBLIC sdk_device)
 add_sdk_driver(clock fsl_clock.c)
 

sdk/devices/MIMXRT1052/drivers/fsl_usdhc.c

@@ -202,6 +202,9 @@ static void USDHC_TransferHandleReTuning(USDHC_Type *base, usdhc_handle_t *handl
 /*******************************************************************************
  * Variables
  ******************************************************************************/
+/* Bring-up telemetry: inspect in debugger watch window. */
+volatile uint32_t g_usdhc_dbg_last_data_interrupt_flags = 0U;
+volatile uint32_t g_usdhc_dbg_last_data_transfer_status = 0U;
 /*! @brief USDHC base pointer array */
 static USDHC_Type *const s_usdhcBase[] = USDHC_BASE_PTRS;
 
@@ -2257,6 +2260,8 @@ static void USDHC_TransferHandleData(USDHC_Type *base, usdhc_handle_t *handle, u
         (IS_USDHC_FLAG_SET(interruptFlags, (uint32_t)kUSDHC_DataErrorFlag | (uint32_t)kUSDHC_DmaErrorFlag)))
     {
         transferStatus = kStatus_USDHC_TransferDataFailed;
+        g_usdhc_dbg_last_data_interrupt_flags = interruptFlags;
+        g_usdhc_dbg_last_data_transfer_status = (uint32_t)transferStatus;
     }
     else
     {
@@ -2315,6 +2320,8 @@ static void USDHC_TransferHandleData(USDHC_Type *base, usdhc_handle_t *handle, u
         (IS_USDHC_FLAG_SET(interruptFlags, (uint32_t)kUSDHC_DataErrorFlag | (uint32_t)kUSDHC_DmaErrorFlag)))
     {
         transferStatus = kStatus_USDHC_TransferDataFailed;
+        g_usdhc_dbg_last_data_interrupt_flags = interruptFlags;
+        g_usdhc_dbg_last_data_transfer_status = (uint32_t)transferStatus;
     }
     else
     {

sdk/middleware/sdmmc/host/usdhc/non_blocking/fsl_sdmmc_host.c

@@ -73,6 +73,12 @@ static status_t SDMMCHOST_ExecuteManualTuning(sdmmchost_t *host,
 /*******************************************************************************
  * Variables
  ******************************************************************************/
+/* Debug telemetry for bring-up: inspect in debugger watch window. */
+volatile uint32_t g_sdmmc_dbg_last_event              = 0U;
+volatile uint32_t g_sdmmc_dbg_last_error              = 0U;
+volatile uint32_t g_sdmmc_dbg_last_irqstat            = 0U;
+volatile uint32_t g_sdmmc_dbg_last_prsstat            = 0U;
+volatile uint32_t g_sdmmc_dbg_last_wait_stage         = 0U; /* 1=cmd wait, 2=data wait */
 
 /*******************************************************************************
  * Code
@@ -511,11 +517,16 @@ status_t SDMMCHOST_TransferFunction(sdmmchost_t *host, sdmmchost_transfer_t *con
     if (error == kStatus_Success)
     {
         /* wait command event */
+        g_sdmmc_dbg_last_wait_stage = 1U;
         if ((kStatus_Fail == SDMMC_OSAEventWait(&(host->hostEvent), SDMMCHOST_TRANSFER_CMD_EVENT,
                                                 SDMMCHOST_TRANSFER_COMPLETE_TIMEOUT, &event)) ||
             ((event & SDMMC_OSA_EVENT_TRANSFER_CMD_FAIL) != 0U))
         {
             error = kStatus_Fail;
+            g_sdmmc_dbg_last_event   = event;
+            g_sdmmc_dbg_last_error   = (uint32_t)error;
+            g_sdmmc_dbg_last_irqstat = USDHC_GetInterruptStatusFlags(host->hostController.base);
+            g_sdmmc_dbg_last_prsstat = USDHC_GetPresentStatusFlags(host->hostController.base);
         }
         else
         {
@@ -523,12 +534,17 @@ status_t SDMMCHOST_TransferFunction(sdmmchost_t *host, sdmmchost_transfer_t *con
             {
                 if ((event & SDMMC_OSA_EVENT_TRANSFER_DATA_SUCCESS) == 0U)
                 {
+                    g_sdmmc_dbg_last_wait_stage = 2U;
                     if (((event & SDMMC_OSA_EVENT_TRANSFER_DATA_FAIL) != 0U) ||
                         (kStatus_Fail == SDMMC_OSAEventWait(&(host->hostEvent), SDMMCHOST_TRANSFER_DATA_EVENT,
                                                             SDMMCHOST_TRANSFER_COMPLETE_TIMEOUT, &event) ||
                          ((event & SDMMC_OSA_EVENT_TRANSFER_DATA_FAIL) != 0U)))
                     {
                         error = kStatus_Fail;
+                        g_sdmmc_dbg_last_event   = event;
+                        g_sdmmc_dbg_last_error   = (uint32_t)error;
+                        g_sdmmc_dbg_last_irqstat = USDHC_GetInterruptStatusFlags(host->hostController.base);
+                        g_sdmmc_dbg_last_prsstat = USDHC_GetPresentStatusFlags(host->hostController.base);
                     }
                 }
             }