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# clock config changed

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This commit is contained in:
Dmitry Akimov 2026-04-01 19:12:05 +03:00
parent 83deac595d
commit 8cd4f20f14
6 changed files with 1707 additions and 0 deletions
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19
bsp/generated/TFT_Board.mex
View file

@ -507,6 +507,7 @@
<clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="TRACE_CLK_ROOT.outFreq" value="6 MHz" locked="false" accuracy=""/> <clock_output id="TRACE_CLK_ROOT.outFreq" value="6 MHz" locked="false" accuracy=""/>
<clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
<clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
<clock_output id="USDHC1_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/> <clock_output id="USDHC1_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/>
<clock_output id="USDHC2_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/> <clock_output id="USDHC2_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/>
</clock_outputs> </clock_outputs>
@ -526,6 +527,8 @@
<setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/> <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/> <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/> <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
<setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
<setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
<setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/> <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
</clock_settings> </clock_settings>
<called_from_default_init>true</called_from_default_init> <called_from_default_init>true</called_from_default_init>
@ -661,6 +664,22 @@
</array> </array>
</config_set> </config_set>
</instance> </instance>
<instance name="USB1" uuid="865ef471-f99f-448e-afba-f6b934300d0f" type="usb" type_id="usb_2.8.0" mode="device" peripheral="USB1" enabled="false" comment="" custom_name_enabled="false" editing_lock="false">
<config_set name="deviceSetting" quick_selection="QS_DEVICE_DEFAULT">
<setting name="vendor_id" value="0x1FC9"/>
<setting name="product_id" value="0x0090"/>
<setting name="manufacturer_string" value="NXP"/>
<setting name="product_string" value="Product"/>
<setting name="self_powered" value="false"/>
<setting name="max_power" value="100"/>
<array name="interfaces"/>
</config_set>
<config_set name="commonSettings">
<struct name="mpu_init">
<setting name="mpu_init_component" value=""/>
</struct>
</config_set>
</instance>
</instances> </instances>
</functional_group> </functional_group>
</functional_groups> </functional_groups>

460
bsp/generated/board/clock_config.c Normal file
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@ -0,0 +1,460 @@
/*
* Copyright 2026 NXP
* All rights reserved.
* MU LLC 2026
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* How to setup clock using clock driver functions:
*
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
*
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
*
* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
*
* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
*
* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
*
*/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v19.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052CVJ5B
mcu_data: ksdk2_0
processor_version: 25.12.10
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
#include "clock_config.h"
#include "fsl_iomuxc.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
- {id: CAN_CLK_ROOT.outFreq, value: 80 MHz}
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CLK_24M.outFreq, value: 24 MHz}
- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 60 MHz}
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
- {id: LCDIF_CLK_ROOT.outFreq, value: 3 MHz}
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
- {id: LPSPI_CLK_ROOT.outFreq, value: 6 MHz}
- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
- {id: SEMC_CLK_ROOT.outFreq, value: 120 MHz}
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
- {id: TRACE_CLK_ROOT.outFreq, value: 6 MHz}
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
- {id: USDHC1_CLK_ROOT.outFreq, value: 12 MHz}
- {id: USDHC2_CLK_ROOT.outFreq, value: 12 MHz}
settings:
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
- {id: CCM.CAN_CLK_PODF.scale, value: '1', locked: true}
- {id: CCM.LCDIF_PRE_CLK_SEL.sel, value: CCM_ANALOG.PLL5_MAIN_CLK}
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
- {id: CCM.PERIPH_CLK2_SEL.sel, value: XTALOSC24M.OSC_CLK}
- {id: CCM.SEMC_PODF.scale, value: '5', locked: true}
- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
sources:
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
.numerator = 1, /* 30 bit numerator of fractional loop divider */
.denominator = 60000, /* 30 bit denominator of fractional loop divider */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
{
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
{
.enableClkOutput = true, /* Enable the PLL providing the ENET 125MHz reference clock */
.enableClkOutput25M = true, /* Enable the PLL providing the ENET 25MHz reference clock */
.loopDivider = 1, /* Set frequency of ethernet reference clock to 2.4 MHz */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
/* Init RTC OSC clock frequency. */
CLOCK_SetRtcXtalFreq(32768U);
/* Enable 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
/* Use free 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
/* Set XTAL 24MHz clock frequency. */
CLOCK_SetXtalFreq(24000000U);
/* Enable XTAL 24MHz clock source. */
CLOCK_InitExternalClk(0);
/* Enable internal RC. */
CLOCK_InitRcOsc24M();
/* Switch clock source to external OSC. */
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
/* Set Oscillator ready counter value. */
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
/* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
/* Waiting for DCDC_STS_DC_OK bit is asserted */
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
{
}
/* Set AHB_PODF. */
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
/* Disable IPG clock gate. */
CLOCK_DisableClock(kCLOCK_Adc1);
CLOCK_DisableClock(kCLOCK_Adc2);
CLOCK_DisableClock(kCLOCK_Xbar1);
CLOCK_DisableClock(kCLOCK_Xbar2);
CLOCK_DisableClock(kCLOCK_Xbar3);
/* Set IPG_PODF. */
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
/* Set ARM_PODF. */
CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
/* Set PERIPH_CLK2_PODF. */
CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
/* Disable PERCLK clock gate. */
CLOCK_DisableClock(kCLOCK_Gpt1);
CLOCK_DisableClock(kCLOCK_Gpt1S);
CLOCK_DisableClock(kCLOCK_Gpt2);
CLOCK_DisableClock(kCLOCK_Gpt2S);
CLOCK_DisableClock(kCLOCK_Pit);
/* Set PERCLK_PODF. */
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
/* Disable USDHC1 clock gate. */
CLOCK_DisableClock(kCLOCK_Usdhc1);
/* Set USDHC1_PODF. */
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
/* Set Usdhc1 clock source. */
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
/* Disable USDHC2 clock gate. */
CLOCK_DisableClock(kCLOCK_Usdhc2);
/* Set USDHC2_PODF. */
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
/* Set Usdhc2 clock source. */
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
/* Disable Semc clock gate. */
CLOCK_DisableClock(kCLOCK_Semc);
/* Set SEMC_PODF. */
CLOCK_SetDiv(kCLOCK_SemcDiv, 4);
/* Set Semc alt clock source. */
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
/* Set Semc clock source. */
CLOCK_SetMux(kCLOCK_SemcMux, 0);
#endif
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Disable Flexspi clock gate. */
CLOCK_DisableClock(kCLOCK_FlexSpi);
/* Set FLEXSPI_PODF. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
/* Set Flexspi clock source. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
#endif
/* Disable CSI clock gate. */
CLOCK_DisableClock(kCLOCK_Csi);
/* Set CSI_PODF. */
CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
/* Set Csi clock source. */
CLOCK_SetMux(kCLOCK_CsiMux, 0);
/* Disable LPSPI clock gate. */
CLOCK_DisableClock(kCLOCK_Lpspi1);
CLOCK_DisableClock(kCLOCK_Lpspi2);
CLOCK_DisableClock(kCLOCK_Lpspi3);
CLOCK_DisableClock(kCLOCK_Lpspi4);
/* Set LPSPI_PODF. */
CLOCK_SetDiv(kCLOCK_LpspiDiv, 3);
/* Set Lpspi clock source. */
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
/* Disable TRACE clock gate. */
CLOCK_DisableClock(kCLOCK_Trace);
/* Set TRACE_PODF. */
CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
/* Set Trace clock source. */
CLOCK_SetMux(kCLOCK_TraceMux, 2);
/* Disable SAI1 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai1);
/* Set SAI1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
/* Set SAI1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
/* Set Sai1 clock source. */
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
/* Disable SAI2 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai2);
/* Set SAI2_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
/* Set SAI2_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
/* Set Sai2 clock source. */
CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
/* Disable SAI3 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai3);
/* Set SAI3_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
/* Set SAI3_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
/* Set Sai3 clock source. */
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
/* Disable Lpi2c clock gate. */
CLOCK_DisableClock(kCLOCK_Lpi2c1);
CLOCK_DisableClock(kCLOCK_Lpi2c2);
CLOCK_DisableClock(kCLOCK_Lpi2c3);
/* Set LPI2C_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
/* Set Lpi2c clock source. */
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
/* Disable CAN clock gate. */
CLOCK_DisableClock(kCLOCK_Can1);
CLOCK_DisableClock(kCLOCK_Can2);
CLOCK_DisableClock(kCLOCK_Can1S);
CLOCK_DisableClock(kCLOCK_Can2S);
/* Set CAN_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_CanDiv, 0);
/* Set Can clock source. */
CLOCK_SetMux(kCLOCK_CanMux, 2);
/* Disable UART clock gate. */
CLOCK_DisableClock(kCLOCK_Lpuart1);
CLOCK_DisableClock(kCLOCK_Lpuart2);
CLOCK_DisableClock(kCLOCK_Lpuart3);
CLOCK_DisableClock(kCLOCK_Lpuart4);
CLOCK_DisableClock(kCLOCK_Lpuart5);
CLOCK_DisableClock(kCLOCK_Lpuart6);
CLOCK_DisableClock(kCLOCK_Lpuart7);
CLOCK_DisableClock(kCLOCK_Lpuart8);
/* Set UART_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
/* Set Uart clock source. */
CLOCK_SetMux(kCLOCK_UartMux, 0);
/* Disable LCDIF clock gate. */
CLOCK_DisableClock(kCLOCK_LcdPixel);
/* Set LCDIF_PRED. */
CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
/* Set LCDIF_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
/* Set Lcdif pre clock source. */
CLOCK_SetMux(kCLOCK_LcdifPreMux, 2);
/* Disable SPDIF clock gate. */
CLOCK_DisableClock(kCLOCK_Spdif);
/* Set SPDIF0_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
/* Set SPDIF0_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
/* Set Spdif clock source. */
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
/* Disable Flexio1 clock gate. */
CLOCK_DisableClock(kCLOCK_Flexio1);
/* Set FLEXIO1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
/* Set FLEXIO1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
/* Set Flexio1 clock source. */
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
/* Disable Flexio2 clock gate. */
CLOCK_DisableClock(kCLOCK_Flexio2);
/* Set FLEXIO2_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
/* Set FLEXIO2_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
/* Set Flexio2 clock source. */
CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
/* Set Pll3 sw clock source. */
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
/* Init ARM PLL. */
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
#warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
#endif
/* Init System PLL. */
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
/* Init System pfd0. */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
/* Init System pfd1. */
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
/* Init System pfd2. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
/* Init System pfd3. */
CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
/* Bypass System PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllSys, 1);
#endif
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Init Usb1 PLL. */
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
/* Init Usb1 pfd0. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 12);
/* Init Usb1 pfd1. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
/* Init Usb1 pfd2. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
/* Init Usb1 pfd3. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
#endif
/* DeInit Audio PLL. */
CLOCK_DeinitAudioPll();
/* Bypass Audio PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
/* Set divider for Audio PLL. */
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
/* Enable Audio PLL output. */
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
/* DeInit Video PLL. */
CLOCK_DeinitVideoPll();
/* Bypass Video PLL. */
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
/* Set divider for Video PLL. */
CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
/* Enable Video PLL output. */
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
/* Init Enet PLL. */
CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
/* Bypass Enet PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
/* DeInit Usb2 PLL. */
CLOCK_DeinitUsb2Pll();
/* Bypass Usb2 PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
/* Enable Usb2 PLL output. */
CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
/* Set preperiph clock source. */
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
/* Set periph clock source. */
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
/* Set periph clock2 clock source. */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1);
/* Set per clock source. */
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
/* Set lvds1 clock source. */
CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
/* Set clock out1 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
/* Set clock out1 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
/* Set clock out2 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
/* Set clock out2 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
/* Set clock out1 drives clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
/* Disable clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
/* Disable clock out2. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
/* Set SAI1 MCLK1 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
/* Set SAI1 MCLK2 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
/* Set SAI1 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
/* Set SAI2 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
/* Set SAI3 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
/* Set MQS configuration. */
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
/* Set ENET Ref clock source. */
#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
/* Backward compatibility for original bitfield name */
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
#else
#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
/* Set GPT1 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
/* Set GPT2 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
}

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/*
* Copyright 2026 NXP
* All rights reserved.
* MU LLC 2026
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 80000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2 */
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET */
#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 60000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, EWM, FLEXIO1, FLEXIO2, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */
#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 3000000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 6000000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */
#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL /* Clock consumers of LVDS1_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */
#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 120000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 6000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */
#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL /* Clock consumers of USBPHY2_CLK output : USB2 */
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 12000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 12000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
*/
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

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/*
* Copyright 2026 NXP
* All rights reserved.
* MU LLC 2026
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v17.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052CVJ5B
mcu_data: ksdk2_0
processor_version: 25.12.10
external_user_signals: {}
pin_labels:
- {pin_num: M4, pin_signal: GPIO_SD_B1_03, label: UserLed1, identifier: LED_1;UserLed1}
- {pin_num: P2, pin_signal: GPIO_SD_B1_04, label: UserLed2, identifier: UserLed2}
- {pin_num: M12, pin_signal: GPIO_AD_B1_03, label: SdPwr, identifier: SdPwr}
- {pin_num: L12, pin_signal: GPIO_AD_B1_04, label: LcdLed, identifier: LcdLed}
- {pin_num: C14, pin_signal: GPIO_B1_14, label: TactBut1, identifier: TactBut1}
- {pin_num: J12, pin_signal: GPIO_AD_B1_06, label: ExtIn1, identifier: ExtIn1}
- {pin_num: K12, pin_signal: GPIO_AD_B1_05, label: ExtIn2, identifier: ExtIn2}
- {pin_num: K10, pin_signal: GPIO_AD_B1_07, label: RsRx, identifier: RsRx}
- {pin_num: H13, pin_signal: GPIO_AD_B1_08, label: VolumeControl, identifier: VolumeControl}
- {pin_num: B14, pin_signal: GPIO_B1_15, label: TactBut2, identifier: TactBut2}
- {pin_num: H12, pin_signal: GPIO_AD_B1_12, label: LcdLR, identifier: LcdLR;LcdLr}
- {pin_num: H11, pin_signal: GPIO_AD_B1_13, label: LcdMode, identifier: LcdMode}
- {pin_num: G12, pin_signal: GPIO_AD_B1_14, label: Lc, identifier: Lc;LcdUd}
- {pin_num: J14, pin_signal: GPIO_AD_B1_15, label: LcdDithb, identifier: LcdDithb}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
#include "fsl_common.h"
#include "fsl_iomuxc.h"
#include "fsl_gpio.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void) {
BOARD_InitPins();
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13}
- {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12}
- {pin_num: L10, peripheral: CAN2, signal: RX, pin_signal: GPIO_AD_B0_15}
- {pin_num: H14, peripheral: CAN2, signal: TX, pin_signal: GPIO_AD_B0_14}
- {pin_num: J3, peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_01}
- {pin_num: J4, peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_00}
- {pin_num: J1, peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_02}
- {pin_num: K1, peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_03}
- {pin_num: H2, peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_04}
- {pin_num: J2, peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_05}
- {pin_num: D13, peripheral: USDHC1, signal: usdhc_cd_b, pin_signal: GPIO_B1_12}
- {pin_num: M4, peripheral: GPIO3, signal: 'gpio_io, 03', pin_signal: GPIO_SD_B1_03, identifier: UserLed1, direction: OUTPUT, gpio_init_state: 'true', pull_keeper_enable: Disable,
drive_strength: R0}
- {pin_num: P2, peripheral: GPIO3, signal: 'gpio_io, 04', pin_signal: GPIO_SD_B1_04, direction: OUTPUT, gpio_init_state: 'true', pull_keeper_select: Keeper, pull_keeper_enable: Disable,
drive_strength: R0}
- {pin_num: M12, peripheral: GPIO1, signal: 'gpio_io, 19', pin_signal: GPIO_AD_B1_03, direction: OUTPUT, gpio_init_state: 'false', pull_keeper_enable: Disable,
drive_strength: R0}
- {pin_num: L12, peripheral: GPIO1, signal: 'gpio_io, 20', pin_signal: GPIO_AD_B1_04, direction: OUTPUT, pull_keeper_enable: Disable, drive_strength: R0}
- {pin_num: F11, peripheral: MQS, signal: RIGHT, pin_signal: GPIO_AD_B0_04}
- {pin_num: C14, peripheral: GPIO2, signal: 'gpio_io, 30', pin_signal: GPIO_B1_14, direction: INPUT, hysteresis_enable: Enable, pull_keeper_enable: Disable}
- {pin_num: J12, peripheral: GPIO1, signal: 'gpio_io, 22', pin_signal: GPIO_AD_B1_06, direction: INPUT, hysteresis_enable: Enable, pull_keeper_enable: Disable}
- {pin_num: K12, peripheral: GPIO1, signal: 'gpio_io, 21', pin_signal: GPIO_AD_B1_05, direction: INPUT, hysteresis_enable: Enable, pull_keeper_enable: Disable}
- {pin_num: H13, peripheral: PWM4, signal: 'A, 0', pin_signal: GPIO_AD_B1_08, direction: OUTPUT, pull_keeper_enable: Disable, drive_strength: R0_2, slew_rate: Fast}
- {pin_num: H12, peripheral: GPIO1, signal: 'gpio_io, 28', pin_signal: GPIO_AD_B1_12, identifier: LcdLr, direction: OUTPUT, pull_keeper_enable: Disable, drive_strength: R0}
- {pin_num: H11, peripheral: GPIO1, signal: 'gpio_io, 29', pin_signal: GPIO_AD_B1_13, direction: OUTPUT, pull_keeper_enable: Disable, drive_strength: R0}
- {pin_num: G12, peripheral: GPIO1, signal: 'gpio_io, 30', pin_signal: GPIO_AD_B1_14, identifier: LcdUd, direction: OUTPUT, pull_keeper_enable: Disable, drive_strength: R0}
- {pin_num: J14, peripheral: GPIO1, signal: 'gpio_io, 31', pin_signal: GPIO_AD_B1_15, direction: OUTPUT, pull_keeper_enable: Disable, drive_strength: R0}
- {pin_num: B14, peripheral: GPIO2, signal: 'gpio_io, 31', pin_signal: GPIO_B1_15, direction: INPUT, hysteresis_enable: Enable, pull_keeper_enable: Disable, drive_strength: R0_6}
- {pin_num: D7, peripheral: LCDIF, signal: lcdif_clk, pin_signal: GPIO_B0_00}
- {pin_num: E7, peripheral: LCDIF, signal: lcdif_enable, pin_signal: GPIO_B0_01}
- {pin_num: E8, peripheral: LCDIF, signal: lcdif_hsync, pin_signal: GPIO_B0_02}
- {pin_num: D8, peripheral: LCDIF, signal: lcdif_vsync, pin_signal: GPIO_B0_03}
- {pin_num: C8, peripheral: LCDIF, signal: 'lcdif_data, 00', pin_signal: GPIO_B0_04}
- {pin_num: B8, peripheral: LCDIF, signal: 'lcdif_data, 01', pin_signal: GPIO_B0_05}
- {pin_num: A8, peripheral: LCDIF, signal: 'lcdif_data, 02', pin_signal: GPIO_B0_06}
- {pin_num: A9, peripheral: LCDIF, signal: 'lcdif_data, 03', pin_signal: GPIO_B0_07}
- {pin_num: B9, peripheral: LCDIF, signal: 'lcdif_data, 04', pin_signal: GPIO_B0_08}
- {pin_num: C9, peripheral: LCDIF, signal: 'lcdif_data, 05', pin_signal: GPIO_B0_09}
- {pin_num: D9, peripheral: LCDIF, signal: 'lcdif_data, 06', pin_signal: GPIO_B0_10}
- {pin_num: A10, peripheral: LCDIF, signal: 'lcdif_data, 07', pin_signal: GPIO_B0_11}
- {pin_num: C10, peripheral: LCDIF, signal: 'lcdif_data, 08', pin_signal: GPIO_B0_12}
- {pin_num: D10, peripheral: LCDIF, signal: 'lcdif_data, 09', pin_signal: GPIO_B0_13}
- {pin_num: E10, peripheral: LCDIF, signal: 'lcdif_data, 10', pin_signal: GPIO_B0_14}
- {pin_num: E11, peripheral: LCDIF, signal: 'lcdif_data, 11', pin_signal: GPIO_B0_15}
- {pin_num: A11, peripheral: LCDIF, signal: 'lcdif_data, 12', pin_signal: GPIO_B1_00}
- {pin_num: B11, peripheral: LCDIF, signal: 'lcdif_data, 13', pin_signal: GPIO_B1_01}
- {pin_num: C11, peripheral: LCDIF, signal: 'lcdif_data, 14', pin_signal: GPIO_B1_02}
- {pin_num: D11, peripheral: LCDIF, signal: 'lcdif_data, 15', pin_signal: GPIO_B1_03}
- {pin_num: E12, peripheral: LCDIF, signal: 'lcdif_data, 16', pin_signal: GPIO_B1_04}
- {pin_num: D12, peripheral: LCDIF, signal: 'lcdif_data, 17', pin_signal: GPIO_B1_05}
- {pin_num: C12, peripheral: LCDIF, signal: 'lcdif_data, 18', pin_signal: GPIO_B1_06}
- {pin_num: B12, peripheral: LCDIF, signal: 'lcdif_data, 19', pin_signal: GPIO_B1_07}
- {pin_num: A12, peripheral: LCDIF, signal: 'lcdif_data, 20', pin_signal: GPIO_B1_08}
- {pin_num: A13, peripheral: LCDIF, signal: 'lcdif_data, 21', pin_signal: GPIO_B1_09}
- {pin_num: B13, peripheral: LCDIF, signal: 'lcdif_data, 22', pin_signal: GPIO_B1_10}
- {pin_num: C13, peripheral: LCDIF, signal: 'lcdif_data, 23', pin_signal: GPIO_B1_11}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
/* GPIO configuration of SdPwr on GPIO_AD_B1_03 (pin M12) */
gpio_pin_config_t SdPwr_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B1_03 (pin M12) */
GPIO_PinInit(GPIO1, 19U, &SdPwr_config);
/* GPIO configuration of LcdLed on GPIO_AD_B1_04 (pin L12) */
gpio_pin_config_t LcdLed_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B1_04 (pin L12) */
GPIO_PinInit(GPIO1, 20U, &LcdLed_config);
/* GPIO configuration of ExtIn2 on GPIO_AD_B1_05 (pin K12) */
gpio_pin_config_t ExtIn2_config = {
.direction = kGPIO_DigitalInput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B1_05 (pin K12) */
GPIO_PinInit(GPIO1, 21U, &ExtIn2_config);
/* GPIO configuration of ExtIn1 on GPIO_AD_B1_06 (pin J12) */
gpio_pin_config_t ExtIn1_config = {
.direction = kGPIO_DigitalInput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B1_06 (pin J12) */
GPIO_PinInit(GPIO1, 22U, &ExtIn1_config);
/* GPIO configuration of LcdLr on GPIO_AD_B1_12 (pin H12) */
gpio_pin_config_t LcdLr_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B1_12 (pin H12) */
GPIO_PinInit(GPIO1, 28U, &LcdLr_config);
/* GPIO configuration of LcdMode on GPIO_AD_B1_13 (pin H11) */
gpio_pin_config_t LcdMode_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B1_13 (pin H11) */
GPIO_PinInit(GPIO1, 29U, &LcdMode_config);
/* GPIO configuration of LcdUd on GPIO_AD_B1_14 (pin G12) */
gpio_pin_config_t LcdUd_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B1_14 (pin G12) */
GPIO_PinInit(GPIO1, 30U, &LcdUd_config);
/* GPIO configuration of LcdDithb on GPIO_AD_B1_15 (pin J14) */
gpio_pin_config_t LcdDithb_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B1_15 (pin J14) */
GPIO_PinInit(GPIO1, 31U, &LcdDithb_config);
/* GPIO configuration of TactBut1 on GPIO_B1_14 (pin C14) */
gpio_pin_config_t TactBut1_config = {
.direction = kGPIO_DigitalInput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_B1_14 (pin C14) */
GPIO_PinInit(GPIO2, 30U, &TactBut1_config);
/* GPIO configuration of TactBut2 on GPIO_B1_15 (pin B14) */
gpio_pin_config_t TactBut2_config = {
.direction = kGPIO_DigitalInput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_B1_15 (pin B14) */
GPIO_PinInit(GPIO2, 31U, &TactBut2_config);
/* GPIO configuration of UserLed1 on GPIO_SD_B1_03 (pin M4) */
gpio_pin_config_t UserLed1_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 1U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_SD_B1_03 (pin M4) */
GPIO_PinInit(GPIO3, 3U, &UserLed1_config);
/* GPIO configuration of UserLed2 on GPIO_SD_B1_04 (pin P2) */
gpio_pin_config_t UserLed2_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 1U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_SD_B1_04 (pin P2) */
GPIO_PinInit(GPIO3, 4U, &UserLed2_config);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_04_MQS_RIGHT, 0U);
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TXD, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
#endif
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_03_GPIO1_IO19, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_04_GPIO1_IO20, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_05_GPIO1_IO21, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, 0U);
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWMA00, 0U);
#endif
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_12_GPIO1_IO28, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_GPIO1_IO29, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_GPIO1_IO30, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_GPIO1_IO31, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_LCD_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_LCD_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_06_LCD_DATA02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_07_LCD_DATA03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_08_LCD_DATA04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_09_LCD_DATA05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_10_LCD_DATA06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_11_LCD_DATA07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_LCD_DATA08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_LCD_DATA09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_LCD_DATA10, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_LCD_DATA11, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LCD_DATA12, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LCD_DATA13, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_LCD_DATA14, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_LCD_DATA16, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_LCD_DATA17, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_LCD_DATA18, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_LCD_DATA19, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_LCD_DATA20, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_LCD_DATA21, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_LCD_DATA22, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_LCD_DATA23, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_12_USDHC1_CD_B, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_14_GPIO2_IO30, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_GPIO3_IO03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_04_GPIO3_IO04, 0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_03_GPIO1_IO19, 0x88U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_04_GPIO1_IO20, 0x88U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_05_GPIO1_IO21, 0x0100B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, 0x0100B0U);
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A, 0x91U);
#else
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWMA00, 0x91U);
#endif
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_12_GPIO1_IO28, 0x88U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_13_GPIO1_IO29, 0x88U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_14_GPIO1_IO30, 0x88U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_15_GPIO1_IO31, 0x88U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_14_GPIO2_IO30, 0x0100B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0x0100B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_03_GPIO3_IO03, 0x88U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_04_GPIO3_IO04, 0x88U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitRS_UART:
- options: {createDeInit: 'true', callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: K10, peripheral: LPUART3, signal: RX, pin_signal: GPIO_AD_B1_07}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitRS_UART
* Description : RS_RX pin is used as LPUART3_RX
*
* END ****************************************************************************************************************/
void BOARD_InitRS_UART(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_LPUART3_RXD, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_LPUART3_RX, 0U);
#endif
}
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitRS_UART_deinit
* Description : This is a de-initialization function for 'BOARD_InitRS_UART' function.
* It sets all pins features (routing, direction and electrical) to their after-reset state.
* It also tries to route the previous peripheral signals to their default pins.
*
* END ****************************************************************************************************************/
void BOARD_InitRS_UART_deinit(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
/* GPIO configuration of RsRx on GPIO_AD_B1_07 (pin K10) */
gpio_pin_config_t RsRx_config = {
.direction = kGPIO_DigitalInput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B1_07 (pin K10) */
GPIO_PinInit(GPIO1, 23U, &RsRx_config);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_GPIO1_IO23, 0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_07_GPIO1_IO23, 0x10B0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitRS_GPIO:
- options: {createDeInit: 'true', callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: K10, peripheral: GPIO1, signal: 'gpio_io, 23', pin_signal: GPIO_AD_B1_07, direction: INPUT, hysteresis_enable: Enable, pull_keeper_enable: Disable}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitRS_GPIO
* Description : RS_RX pin is used as GPIO_INPUT
*
* END ****************************************************************************************************************/
void BOARD_InitRS_GPIO(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
/* GPIO configuration of RsRx on GPIO_AD_B1_07 (pin K10) */
gpio_pin_config_t RsRx_config = {
.direction = kGPIO_DigitalInput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B1_07 (pin K10) */
GPIO_PinInit(GPIO1, 23U, &RsRx_config);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_GPIO1_IO23, 0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_07_GPIO1_IO23, 0x0100B0U);
}
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitRS_GPIO_deinit
* Description : This is a de-initialization function for 'BOARD_InitRS_GPIO' function.
* It sets all pins features (routing, direction and electrical) to their after-reset state.
* It also tries to route the previous peripheral signals to their default pins.
*
* END ****************************************************************************************************************/
void BOARD_InitRS_GPIO_deinit(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
/* GPIO configuration of RsRx on GPIO_AD_B1_07 (pin K10) */
gpio_pin_config_t RsRx_config = {
.direction = kGPIO_DigitalInput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B1_07 (pin K10) */
GPIO_PinInit(GPIO1, 23U, &RsRx_config);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_GPIO1_IO23, 0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_07_GPIO1_IO23, 0x10B0U);
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

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bsp/generated/board/pin_mux.h Normal file
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@ -0,0 +1,362 @@
/*
* Copyright 2026 NXP
* All rights reserved.
* MU LLC 2026
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/***********************************************************************************************************************
* Definitions
**********************************************************************************************************************/
/*! @brief Direction type */
typedef enum _pin_mux_direction
{
kPIN_MUX_DirectionInput = 0U, /* Input direction */
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
} pin_mux_direction_t;
/*!
* @addtogroup pin_mux
* @{
*/
/***********************************************************************************************************************
* API
**********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
/* GPIO_SD_B1_03 (coord M4), UserLed1 */
/* Routed pin properties */
#define BOARD_INITPINS_UserLed1_PERIPHERAL GPIO3 /*!< Peripheral name */
#define BOARD_INITPINS_UserLed1_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_UserLed1_CHANNEL 3U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_UserLed1_GPIO GPIO3 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_UserLed1_INIT_GPIO_VALUE 1U /*!< GPIO output initial state */
#define BOARD_INITPINS_UserLed1_GPIO_PIN 3U /*!< GPIO pin number */
#define BOARD_INITPINS_UserLed1_GPIO_PIN_MASK (1U << 3U) /*!< GPIO pin mask */
#define BOARD_INITPINS_UserLed1_PORT GPIO3 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_UserLed1_PIN 3U /*!< PORT pin number */
#define BOARD_INITPINS_UserLed1_PIN_MASK (1U << 3U) /*!< PORT pin mask */
/* GPIO_SD_B1_04 (coord P2), UserLed2 */
/* Routed pin properties */
#define BOARD_INITPINS_UserLed2_PERIPHERAL GPIO3 /*!< Peripheral name */
#define BOARD_INITPINS_UserLed2_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_UserLed2_CHANNEL 4U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_UserLed2_GPIO GPIO3 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_UserLed2_INIT_GPIO_VALUE 1U /*!< GPIO output initial state */
#define BOARD_INITPINS_UserLed2_GPIO_PIN 4U /*!< GPIO pin number */
#define BOARD_INITPINS_UserLed2_GPIO_PIN_MASK (1U << 4U) /*!< GPIO pin mask */
#define BOARD_INITPINS_UserLed2_PORT GPIO3 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_UserLed2_PIN 4U /*!< PORT pin number */
#define BOARD_INITPINS_UserLed2_PIN_MASK (1U << 4U) /*!< PORT pin mask */
/* GPIO_AD_B1_03 (coord M12), SdPwr */
/* Routed pin properties */
#define BOARD_INITPINS_SdPwr_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITPINS_SdPwr_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_SdPwr_CHANNEL 19U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_SdPwr_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_SdPwr_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */
#define BOARD_INITPINS_SdPwr_GPIO_PIN 19U /*!< GPIO pin number */
#define BOARD_INITPINS_SdPwr_GPIO_PIN_MASK (1U << 19U) /*!< GPIO pin mask */
#define BOARD_INITPINS_SdPwr_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_SdPwr_PIN 19U /*!< PORT pin number */
#define BOARD_INITPINS_SdPwr_PIN_MASK (1U << 19U) /*!< PORT pin mask */
/* GPIO_AD_B1_04 (coord L12), LcdLed */
/* Routed pin properties */
#define BOARD_INITPINS_LcdLed_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITPINS_LcdLed_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_LcdLed_CHANNEL 20U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_LcdLed_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_LcdLed_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */
#define BOARD_INITPINS_LcdLed_GPIO_PIN 20U /*!< GPIO pin number */
#define BOARD_INITPINS_LcdLed_GPIO_PIN_MASK (1U << 20U) /*!< GPIO pin mask */
#define BOARD_INITPINS_LcdLed_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_LcdLed_PIN 20U /*!< PORT pin number */
#define BOARD_INITPINS_LcdLed_PIN_MASK (1U << 20U) /*!< PORT pin mask */
/* GPIO_B1_14 (coord C14), TactBut1 */
/* Routed pin properties */
#define BOARD_INITPINS_TactBut1_PERIPHERAL GPIO2 /*!< Peripheral name */
#define BOARD_INITPINS_TactBut1_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_TactBut1_CHANNEL 30U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_TactBut1_GPIO GPIO2 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_TactBut1_GPIO_PIN 30U /*!< GPIO pin number */
#define BOARD_INITPINS_TactBut1_GPIO_PIN_MASK (1U << 30U) /*!< GPIO pin mask */
#define BOARD_INITPINS_TactBut1_PORT GPIO2 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_TactBut1_PIN 30U /*!< PORT pin number */
#define BOARD_INITPINS_TactBut1_PIN_MASK (1U << 30U) /*!< PORT pin mask */
/* GPIO_AD_B1_06 (coord J12), ExtIn1 */
/* Routed pin properties */
#define BOARD_INITPINS_ExtIn1_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITPINS_ExtIn1_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_ExtIn1_CHANNEL 22U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_ExtIn1_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_ExtIn1_GPIO_PIN 22U /*!< GPIO pin number */
#define BOARD_INITPINS_ExtIn1_GPIO_PIN_MASK (1U << 22U) /*!< GPIO pin mask */
#define BOARD_INITPINS_ExtIn1_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_ExtIn1_PIN 22U /*!< PORT pin number */
#define BOARD_INITPINS_ExtIn1_PIN_MASK (1U << 22U) /*!< PORT pin mask */
/* GPIO_AD_B1_05 (coord K12), ExtIn2 */
/* Routed pin properties */
#define BOARD_INITPINS_ExtIn2_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITPINS_ExtIn2_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_ExtIn2_CHANNEL 21U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_ExtIn2_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_ExtIn2_GPIO_PIN 21U /*!< GPIO pin number */
#define BOARD_INITPINS_ExtIn2_GPIO_PIN_MASK (1U << 21U) /*!< GPIO pin mask */
#define BOARD_INITPINS_ExtIn2_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_ExtIn2_PIN 21U /*!< PORT pin number */
#define BOARD_INITPINS_ExtIn2_PIN_MASK (1U << 21U) /*!< PORT pin mask */
/* GPIO_AD_B1_08 (coord H13), VolumeControl */
/* Routed pin properties */
#define BOARD_INITPINS_VolumeControl_PERIPHERAL PWM4 /*!< Peripheral name */
#define BOARD_INITPINS_VolumeControl_SIGNAL A /*!< Signal name */
#define BOARD_INITPINS_VolumeControl_CHANNEL 0U /*!< Signal channel */
/* GPIO_AD_B1_12 (coord H12), LcdLR */
/* Routed pin properties */
#define BOARD_INITPINS_LcdLr_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITPINS_LcdLr_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_LcdLr_CHANNEL 28U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_LcdLr_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_LcdLr_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */
#define BOARD_INITPINS_LcdLr_GPIO_PIN 28U /*!< GPIO pin number */
#define BOARD_INITPINS_LcdLr_GPIO_PIN_MASK (1U << 28U) /*!< GPIO pin mask */
#define BOARD_INITPINS_LcdLr_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_LcdLr_PIN 28U /*!< PORT pin number */
#define BOARD_INITPINS_LcdLr_PIN_MASK (1U << 28U) /*!< PORT pin mask */
/* GPIO_AD_B1_13 (coord H11), LcdMode */
/* Routed pin properties */
#define BOARD_INITPINS_LcdMode_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITPINS_LcdMode_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_LcdMode_CHANNEL 29U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_LcdMode_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_LcdMode_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */
#define BOARD_INITPINS_LcdMode_GPIO_PIN 29U /*!< GPIO pin number */
#define BOARD_INITPINS_LcdMode_GPIO_PIN_MASK (1U << 29U) /*!< GPIO pin mask */
#define BOARD_INITPINS_LcdMode_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_LcdMode_PIN 29U /*!< PORT pin number */
#define BOARD_INITPINS_LcdMode_PIN_MASK (1U << 29U) /*!< PORT pin mask */
/* GPIO_AD_B1_14 (coord G12), Lc */
/* Routed pin properties */
#define BOARD_INITPINS_LcdUd_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITPINS_LcdUd_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_LcdUd_CHANNEL 30U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_LcdUd_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_LcdUd_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */
#define BOARD_INITPINS_LcdUd_GPIO_PIN 30U /*!< GPIO pin number */
#define BOARD_INITPINS_LcdUd_GPIO_PIN_MASK (1U << 30U) /*!< GPIO pin mask */
#define BOARD_INITPINS_LcdUd_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_LcdUd_PIN 30U /*!< PORT pin number */
#define BOARD_INITPINS_LcdUd_PIN_MASK (1U << 30U) /*!< PORT pin mask */
/* GPIO_AD_B1_15 (coord J14), LcdDithb */
/* Routed pin properties */
#define BOARD_INITPINS_LcdDithb_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITPINS_LcdDithb_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_LcdDithb_CHANNEL 31U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_LcdDithb_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_LcdDithb_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */
#define BOARD_INITPINS_LcdDithb_GPIO_PIN 31U /*!< GPIO pin number */
#define BOARD_INITPINS_LcdDithb_GPIO_PIN_MASK (1U << 31U) /*!< GPIO pin mask */
#define BOARD_INITPINS_LcdDithb_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_LcdDithb_PIN 31U /*!< PORT pin number */
#define BOARD_INITPINS_LcdDithb_PIN_MASK (1U << 31U) /*!< PORT pin mask */
/* GPIO_B1_15 (coord B14), TactBut2 */
/* Routed pin properties */
#define BOARD_INITPINS_TactBut2_PERIPHERAL GPIO2 /*!< Peripheral name */
#define BOARD_INITPINS_TactBut2_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_TactBut2_CHANNEL 31U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_TactBut2_GPIO GPIO2 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_TactBut2_GPIO_PIN 31U /*!< GPIO pin number */
#define BOARD_INITPINS_TactBut2_GPIO_PIN_MASK (1U << 31U) /*!< GPIO pin mask */
#define BOARD_INITPINS_TactBut2_PORT GPIO2 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_TactBut2_PIN 31U /*!< PORT pin number */
#define BOARD_INITPINS_TactBut2_PIN_MASK (1U << 31U) /*!< PORT pin mask */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitPins(void);
/* GPIO_AD_B1_07 (coord K10), RsRx */
/* Routed pin properties */
#define BOARD_INITRS_UART_RsRx_PERIPHERAL LPUART3 /*!< Peripheral name */
#define BOARD_INITRS_UART_RsRx_SIGNAL RX /*!< Signal name */
/*!
* @brief RS_RX pin is used as LPUART3_RX
*
*/
void BOARD_InitRS_UART(void);
/* GPIO_AD_B1_07 (coord K10), RsRx */
/* Routed pin properties */
#define BOARD_INITRS_UART_DEINIT_RsRx_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITRS_UART_DEINIT_RsRx_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITRS_UART_DEINIT_RsRx_CHANNEL 23U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITRS_UART_DEINIT_RsRx_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITRS_UART_DEINIT_RsRx_GPIO_PIN 23U /*!< GPIO pin number */
#define BOARD_INITRS_UART_DEINIT_RsRx_GPIO_PIN_MASK (1U << 23U) /*!< GPIO pin mask */
#define BOARD_INITRS_UART_DEINIT_RsRx_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITRS_UART_DEINIT_RsRx_PIN 23U /*!< PORT pin number */
#define BOARD_INITRS_UART_DEINIT_RsRx_PIN_MASK (1U << 23U) /*!< PORT pin mask */
/* GPIO_AD_B1_07 (coord K10), RsRx */
/* Routed pin properties */
#define BOARD_INITRS_UART_DEINIT_RsRx_PERIPHERAL ADC2 /*!< Peripheral name */
#define BOARD_INITRS_UART_DEINIT_RsRx_SIGNAL IN /*!< Signal name */
#define BOARD_INITRS_UART_DEINIT_RsRx_CHANNEL 12U /*!< Signal channel */
/* GPIO_AD_B1_07 (coord K10), RsRx */
/* Routed pin properties */
#define BOARD_INITRS_UART_DEINIT_RsRx_PERIPHERAL CMP1 /*!< Peripheral name */
#define BOARD_INITRS_UART_DEINIT_RsRx_SIGNAL IN /*!< Signal name */
#define BOARD_INITRS_UART_DEINIT_RsRx_CHANNEL 5U /*!< Signal channel */
/* GPIO_AD_B1_07 (coord K10) */
/* Routed pin properties */
#define BOARD_INITRS_UART_DEINIT_RsRx_PERIPHERAL ADC1 /*!< Peripheral name */
#define BOARD_INITRS_UART_DEINIT_RsRx_SIGNAL IN /*!< Signal name */
#define BOARD_INITRS_UART_DEINIT_RsRx_CHANNEL 12U /*!< Signal channel */
/*!
* @brief This is a de-initialization function for 'BOARD_InitRS_UART' function.
* It sets all pins features (routing, direction and electrical) to their after-reset state.
* It also tries to route the previous peripheral signals to their default pins.
*
*/
void BOARD_InitRS_UART_deinit(void);
/* GPIO_AD_B1_07 (coord K10), RsRx */
/* Routed pin properties */
#define BOARD_INITRS_GPIO_RsRx_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITRS_GPIO_RsRx_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITRS_GPIO_RsRx_CHANNEL 23U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITRS_GPIO_RsRx_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITRS_GPIO_RsRx_GPIO_PIN 23U /*!< GPIO pin number */
#define BOARD_INITRS_GPIO_RsRx_GPIO_PIN_MASK (1U << 23U) /*!< GPIO pin mask */
#define BOARD_INITRS_GPIO_RsRx_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITRS_GPIO_RsRx_PIN 23U /*!< PORT pin number */
#define BOARD_INITRS_GPIO_RsRx_PIN_MASK (1U << 23U) /*!< PORT pin mask */
/*!
* @brief RS_RX pin is used as GPIO_INPUT
*
*/
void BOARD_InitRS_GPIO(void);
/* GPIO_AD_B1_07 (coord K10), RsRx */
/* Routed pin properties */
#define BOARD_INITRS_GPIO_DEINIT_RsRx_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITRS_GPIO_DEINIT_RsRx_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITRS_GPIO_DEINIT_RsRx_CHANNEL 23U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITRS_GPIO_DEINIT_RsRx_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITRS_GPIO_DEINIT_RsRx_GPIO_PIN 23U /*!< GPIO pin number */
#define BOARD_INITRS_GPIO_DEINIT_RsRx_GPIO_PIN_MASK (1U << 23U) /*!< GPIO pin mask */
#define BOARD_INITRS_GPIO_DEINIT_RsRx_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITRS_GPIO_DEINIT_RsRx_PIN 23U /*!< PORT pin number */
#define BOARD_INITRS_GPIO_DEINIT_RsRx_PIN_MASK (1U << 23U) /*!< PORT pin mask */
/* GPIO_AD_B1_07 (coord K10), RsRx */
/* Routed pin properties */
#define BOARD_INITRS_GPIO_DEINIT_RsRx_PERIPHERAL ADC2 /*!< Peripheral name */
#define BOARD_INITRS_GPIO_DEINIT_RsRx_SIGNAL IN /*!< Signal name */
#define BOARD_INITRS_GPIO_DEINIT_RsRx_CHANNEL 12U /*!< Signal channel */
/* GPIO_AD_B1_07 (coord K10), RsRx */
/* Routed pin properties */
#define BOARD_INITRS_GPIO_DEINIT_RsRx_PERIPHERAL CMP1 /*!< Peripheral name */
#define BOARD_INITRS_GPIO_DEINIT_RsRx_SIGNAL IN /*!< Signal name */
#define BOARD_INITRS_GPIO_DEINIT_RsRx_CHANNEL 5U /*!< Signal channel */
/* GPIO_AD_B1_07 (coord K10) */
/* Routed pin properties */
#define BOARD_INITRS_GPIO_DEINIT_RsRx_PERIPHERAL ADC1 /*!< Peripheral name */
#define BOARD_INITRS_GPIO_DEINIT_RsRx_SIGNAL IN /*!< Signal name */
#define BOARD_INITRS_GPIO_DEINIT_RsRx_CHANNEL 12U /*!< Signal channel */
/*!
* @brief This is a de-initialization function for 'BOARD_InitRS_GPIO' function.
* It sets all pins features (routing, direction and electrical) to their after-reset state.
* It also tries to route the previous peripheral signals to their default pins.
*
*/
void BOARD_InitRS_GPIO_deinit(void);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

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.
├── CMakeLists.txt
├── CMakePresets.json
├── Justfile
├── README.md
├── bootstrap.sh
├── bsp
│   ├── CMakeLists.txt
│   ├── README.md
│   ├── button
│   │   ├── CMakeLists.txt
│   │   ├── README.md
│   │   ├── include
│   │   └── src
│   ├── can
│   │   ├── CMakeLists.txt
│   │   ├── README.md
│   │   ├── include
│   │   ├── mocks
│   │   └── src
│   ├── common
│   │   ├── CMakeLists.txt
│   │   └── include
│   ├── generated
│   │   ├── README.md
│   │   ├── TFT_Board.mex
│   │   ├── board
│   │   ├── board.c
│   │   ├── board.h
│   │   ├── clock_config.c
│   │   ├── clock_config.h
│   │   ├── pin_mux.c
│   │   ├── pin_mux.h
│   │   ├── startup
│   │   └── syscalls.c
│   ├── led
│   │   ├── CMakeLists.txt
│   │   ├── README.md
│   │   ├── include
│   │   └── src
│   ├── opto
│   │   ├── CMakeLists.txt
│   │   ├── README.md
│   │   ├── include
│   │   └── src
│   ├── sdram
│   │   ├── README.md
│   │   ├── include
│   │   └── src
│   ├── tick
│   │   ├── CMakeLists.txt
│   │   ├── README.md
│   │   ├── include
│   │   └── src
│   ├── uart_host
│   │   ├── CMakeLists.txt
│   │   ├── README.md
│   │   ├── include
│   │   ├── mocks
│   │   └── src
│   └── usb_cdc
│   ├── CMakeLists.txt
│   ├── README.md
│   ├── include
│   └── src
├── build
│   ├── Debug
│   │   ├── CMakeCache.txt
│   │   ├── CMakeFiles
│   │   ├── bsp
│   │   ├── build.ninja
│   │   ├── cmake_install.cmake
│   │   ├── compile_commands.json
│   │   ├── firmware
│   │   ├── firmware_test.bin
│   │   ├── firmware_test.elf
│   │   ├── firmware_test.map
│   │   ├── firmware_test_hab.bin
│   │   ├── lib
│   │   ├── port
│   │   ├── sdk
│   │   └── utils
│   ├── host-debug
│   │   ├── CMakeCache.txt
│   │   ├── CMakeFiles
│   │   ├── CTestTestfile.cmake
│   │   ├── Testing
│   │   ├── bsp
│   │   ├── build.ninja
│   │   ├── cmake_install.cmake
│   │   ├── compile_commands.json
│   │   ├── lib
│   │   ├── port
│   │   ├── sdk
│   │   ├── tests
│   │   └── utils
│   └── host-release
│   ├── CMakeCache.txt
│   ├── CMakeFiles
│   ├── CTestTestfile.cmake
│   ├── Testing
│   ├── bsp
│   ├── build.ninja
│   ├── cmake_install.cmake
│   ├── compile_commands.json
│   ├── lib
│   ├── port
│   ├── sdk
│   ├── tests
│   └── utils
├── cmake
│   ├── linker
│   │   ├── MIMXRT1052xxxxx_flexspi_nor.ld
│   │   ├── MIMXRT1052xxxxx_flexspi_nor_sdram.ld
│   │   ├── MIMXRT1052xxxxx_ram.ld
│   │   ├── MIMXRT1052xxxxx_sdram.ld
│   │   └── MIMXRT1052xxxxx_sdram_txt.ld
│   ├── toolchain_arm.cmake
│   └── toolchain_host.cmake
├── docs
│   ├── DEV_ARCH.md
│   ├── HOW_TO_DEBUG.md
│   ├── HOW_TO_FLASH.md
│   ├── hardware
│   │   ├── MCULINKINSERT.pdf
│   │   ├── board
│   │   └── m5stamPLC
│   ├── mimxrt1052
│   │   ├── BOOT_FLAGS.md
│   │   ├── HAB_GUIDE.md
│   │   ├── manufacturing_user's_guide.pdf
│   │   └── mcu_rm.pdf
│   └── testing
│   ├── hil
│   └── host
├── firmware
│   ├── bootloader
│   ├── test
│   │   ├── CMakeLists.txt
│   │   ├── README.md
│   │   ├── arch.svg
│   │   └── main.c
│   └── tft_app
├── just
│   ├── build.just
│   ├── ci.just
│   └── host.just
├── lib
│   ├── CMakeLists.txt
│   ├── SEGGER
│   │   ├── RTT
│   │   └── wrapper
│   ├── Unity
│   │   ├── CMakeLists.txt
│   │   ├── LICENSE.txt
│   │   ├── README.md
│   │   ├── auto
│   │   ├── docs
│   │   ├── examples
│   │   ├── extras
│   │   ├── library.json
│   │   ├── meson.build
│   │   ├── meson_options.txt
│   │   ├── platformio-build.py
│   │   ├── src
│   │   ├── test
│   │   └── unityConfig.cmake
│   └── fff
│   ├── CMakeLists.txt
│   ├── LICENSE
│   ├── README.md
│   ├── buildandtest
│   ├── examples
│   ├── fakegen.rb
│   ├── fff.h
│   └── test
├── port
│   ├── CMakeLists.txt
│   ├── README.md
│   └── log
│   ├── CMakeLists.txt
│   ├── README.md
│   ├── include
│   └── src
├── project_tree.txt
├── pyocd.yaml
├── pyocd_debug.yaml
├── sdk
│   ├── CMSIS
│   │   ├── Core
│   │   ├── DSP
│   │   ├── Driver
│   │   ├── LICENSE.txt
│   │   ├── NN
│   │   └── RTOS2
│   ├── CMakeLists.txt
│   ├── COPYING-BSD-3
│   ├── LA_OPT_NXP_Software_License.txt
│   ├── MIMXRT1052xxxxB_manifest_v3_15.xml
│   ├── README.md
│   ├── SW-Content-Register.txt
│   ├── boards
│   │   └── evkbimxrt1050
│   ├── components
│   │   ├── audio
│   │   ├── button
│   │   ├── codec
│   │   ├── common_task
│   │   ├── crc
│   │   ├── display
│   │   ├── exception_handling
│   │   ├── flash
│   │   ├── gpio
│   │   ├── i2c
│   │   ├── internal_flash
│   │   ├── led
│   │   ├── lists
│   │   ├── log
│   │   ├── mem_manager
│   │   ├── messaging
│   │   ├── mx25r_flash
│   │   ├── osa
│   │   ├── panic
│   │   ├── phy
│   │   ├── pmic
│   │   ├── reset
│   │   ├── rng
│   │   ├── rtt
│   │   ├── sensor
│   │   ├── serial_manager
│   │   ├── silicon_id
│   │   ├── spi
│   │   ├── timer
│   │   ├── timer_manager
│   │   ├── touch
│   │   ├── uart
│   │   ├── video
│   │   └── wifi_bt_module
│   ├── devices
│   │   └── MIMXRT1052
│   ├── docs
│   │   └── readme.md
│   ├── middleware
│   │   ├── audio_voice
│   │   ├── cjson
│   │   ├── dhara
│   │   ├── fatfs
│   │   ├── freemaster
│   │   ├── libjpeg
│   │   ├── littlefs
│   │   ├── mcuboot_opensource
│   │   ├── pkcs11
│   │   ├── pngdec
│   │   ├── sdmmc
│   │   ├── tfm
│   │   ├── tinycbor
│   │   └── usb
│   ├── rtos
│   │   └── freertos
│   └── tools
│   └── cmake_toolchain_files
├── tests
│   ├── CMakeLists.txt
│   ├── host
│   │   ├── CMakeLists.txt
│   │   ├── README.md
│   │   ├── button
│   │   ├── can
│   │   ├── led
│   │   ├── log
│   │   ├── mocks
│   │   ├── opto
│   │   ├── ring_buffer
│   │   ├── timeout
│   │   └── uart_host
│   └── target
│   ├── CMakeLists.txt
│   ├── hil_button
│   ├── hil_can
│   ├── hil_opto
│   └── host_uart
├── tools
│   ├── hil
│   │   ├── 01_test_uart.py
│   │   ├── 02_test_opto.py
│   │   ├── 03_test_can.py
│   │   ├── 04_test_button.py
│   │   ├── README.md
│   │   ├── __pycache__
│   │   ├── conftest.py
│   │   ├── env_config.py
│   │   ├── load_and_run.py
│   │   ├── m5
│   │   ├── pyocd_utils.py
│   │   ├── pyproject.toml
│   │   └── uv.lock
│   └── host
│   ├── README.md
│   ├── dcd
│   ├── flash_swd.py
│   ├── flash_usb.py
│   ├── hab
│   ├── pyproject.toml
│   └── uv.lock
└── utils
├── CMakeLists.txt
├── README.md
├── log
│   ├── README.md
│   ├── log.c
│   └── log.h
└── ring_buffer
├── README.md
├── ring_buffer.c
└── ring_buffer.h
185 directories, 130 files