115 lines
4.2 KiB
C
115 lines
4.2 KiB
C
#include "board.h"
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#include "clock_config.h"
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#include "core_cm7.h"
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#include "fsl_common.h"
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#include "pin_mux.h"
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/* Non-cacheable region boundaries — exported by linker script */
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extern uint32_t __NCACHE_REGION_START[];
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extern uint32_t __NCACHE_REGION_SIZE[];
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/*! @brief Конфигурация MPU: регионы памяти, атрибуты кэширования.
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*
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* Должна вызываться до включения D-Cache/I-Cache.
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* Конкретный набор регионов определяется макросами времени сборки:
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* - XIP_EXTERNAL_FLASH — добавляет cacheable RO регион для FlexSPI NOR
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* - BOARD_MPU_SDRAM — добавляет cacheable RW регион для SDRAM 32 MB
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*
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* После возврата MPU включён, D-Cache и I-Cache включены.
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*/
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static void board_mpu_init(void)
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{
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uint32_t nc_start = (uint32_t) __NCACHE_REGION_START;
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uint32_t nc_size = (uint32_t) __NCACHE_REGION_SIZE;
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volatile uint32_t i = 0U;
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if ((SCB->CCR & SCB_CCR_IC_Msk) != 0U)
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{
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SCB_DisableICache();
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}
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if ((SCB->CCR & SCB_CCR_DC_Msk) != 0U)
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{
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SCB_DisableDCache();
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}
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ARM_MPU_Disable();
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/* Region 0: deny-all, Strongly Ordered — errata 1013783-B workaround. */
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MPU->RBAR = ARM_MPU_RBAR(0U, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_NONE, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_4GB);
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/* Region 1: Device, 0x80000000, 512 MB. */
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MPU->RBAR = ARM_MPU_RBAR(1U, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0U, ARM_MPU_AP_FULL, 2U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_512MB);
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/* Region 2: Device, 0x60000000, 512 MB. */
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MPU->RBAR = ARM_MPU_RBAR(2U, 0x60000000U);
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MPU->RASR = ARM_MPU_RASR(0U, ARM_MPU_AP_FULL, 2U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_512MB);
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#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
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/* Region 3: Normal WB, RO, XIP — overrides Region 2 for Flash 64 MB. */
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MPU->RBAR = ARM_MPU_RBAR(3U, 0x60000000U);
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MPU->RASR = ARM_MPU_RASR(0U, ARM_MPU_AP_RO, 0U, 0U, 1U, 1U, 0U, ARM_MPU_REGION_SIZE_64MB);
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#endif
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/* Region 4: Device, 0x00000000, 1 GB. */
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MPU->RBAR = ARM_MPU_RBAR(4U, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(0U, ARM_MPU_AP_FULL, 2U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_1GB);
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/* Region 5: Normal WB, ITCM 128 KB — overrides Region 4. */
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MPU->RBAR = ARM_MPU_RBAR(5U, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(0U, ARM_MPU_AP_FULL, 0U, 0U, 1U, 1U, 0U, ARM_MPU_REGION_SIZE_128KB);
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/* Region 6: Normal WB, DTCM 128 KB. */
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MPU->RBAR = ARM_MPU_RBAR(6U, 0x20000000U);
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MPU->RASR = ARM_MPU_RASR(0U, ARM_MPU_AP_FULL, 0U, 0U, 1U, 1U, 0U, ARM_MPU_REGION_SIZE_128KB);
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/* Region 7: Normal WB, OCRAM 256 KB. */
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MPU->RBAR = ARM_MPU_RBAR(7U, 0x20200000U);
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MPU->RASR = ARM_MPU_RASR(0U, ARM_MPU_AP_FULL, 0U, 0U, 1U, 1U, 0U, ARM_MPU_REGION_SIZE_256KB);
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#if defined(BOARD_MPU_SDRAM) && (BOARD_MPU_SDRAM == 1)
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/* Region 8: Normal WB, SDRAM 32 MB — overrides Region 1. */
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MPU->RBAR = ARM_MPU_RBAR(8U, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0U, ARM_MPU_AP_FULL, 0U, 0U, 1U, 1U, 0U, ARM_MPU_REGION_SIZE_32MB);
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#endif
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/* Region 9: Non-cacheable OCRAM — overrides Region 7 for USB DMA. */
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while ((nc_size >> i) > 1U)
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{
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i++;
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}
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if (i != 0U)
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{
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MPU->RBAR = ARM_MPU_RBAR(9U, nc_start);
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MPU->RASR = ARM_MPU_RASR(0U, ARM_MPU_AP_FULL, 1U, 0U, 0U, 0U, 0U, i - 1U);
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}
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/* Region 10: Device, peripherals 0x40000000, 4 MB. */
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MPU->RBAR = ARM_MPU_RBAR(10U, 0x40000000U);
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MPU->RASR = ARM_MPU_RASR(0U, ARM_MPU_AP_FULL, 2U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_4MB);
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ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
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SCB_EnableDCache();
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SCB_EnableICache();
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}
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static void board_dwt_init(void)
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{
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/* DWT cycle counter — нужен для точного SDK_DelayAtLeastUs.
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* Без этого SDK использует software loop с непредсказуемым timing. */
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CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
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DWT->CYCCNT = 0U;
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DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
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}
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void board_hw_init(void)
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{
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board_dwt_init();
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BOARD_InitPins();
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BOARD_BootClockRUN();
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board_mpu_init();
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}
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